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HMD2M32M4EG-6 Datasheet(PDF) 4 Page - Hanbit Electronics Co.,Ltd |
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HMD2M32M4EG-6 Datasheet(HTML) 4 Page - Hanbit Electronics Co.,Ltd |
4 / 7 page HANBit HMD2M32M4E/4EG URL:www.hbe.co.kr HANBit Electronics Co.,Ltd. REV.1.0 (August.2002) 9 ICC4 : Fast Page Mode Current * (/RAS=VIL, /CAS, Address cycling @tPC=min ) ICC5 : Standby Current (/RAS=/CAS=Vcc-0.2V ) ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @tRC=min ) IIL : Input Leakage Current (Any input 0V £ VIN £ 6.5V, all other pins not under test = 0V) IOL : Output Leakage Current (Data out is disabled, 0V £ VOUT £ 5.5V VOH : Output High Voltage Level (IOH= -5mA ) VOL : Output Low Voltage Level (IOL = 4.2mA ) * NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained wi th the output open. ICC is specified as an average current. In I CC1 and ICC3, address cad be changed maximum once while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle. CAPACITANCE ( TA=25 o C, Vcc = 5V, f = 1Mz ) DESCRIPTION SYMBOL MIN MAX UNITS Input Capacitance (A0-A10) CIN1 - 44 pF Input Capacitance (/W) C IN2 - 48 pF Input Capacitance (/RAS0) CIN3 - 40 pF Input Capacitance (/CAS0-/CAS3) CIN4 - 29 pF Input/Output Capacitance (DQ0-31) CDQ1 - 29 pF AC CHARACTERISTICS ( 0 o C £ TA £ 70oC , Vcc = 5V±10%, See notes 1,2.) -5 -6 STANDARD OPERATION SYMBOL MIN MAX MIN MAX UNIT Random read or write cycle time tRC 90 110 ns Access time from /RAS tRAC 50 60 ns Access time from /CAS tCAC 15 17 ns Access time from column address tAA 25 30 ns /CAS to output in Low-Z tCLZ 3 3 ns Output buffer turn-off delay tOFF 3 13 3 15 ns Transition time (rise and fall) tT 2 50 2 50 ns /RAS precharge time tRP 30 40 ns /RAS pulse width tRAS 50 10K 60 10K ns /RAS hold time tRSH 13 17 ns /CAS hold time tCSH 40 50 ns /CAS pulse width tCAS 8 10K 10 10K ns /RAS to /CAS delay time tRCD 20 37 20 45 ns /RAS to column address delay time tRAD 15 25 15 30 ns /CAS to /RAS precharge time tCRP 5 5 ns Row address set-up time tASR 0 0 ns Row address hold time tRAH 10 10 ns |
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