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HMD4M1Z1-6 Datasheet(PDF) 4 Page - Hanbit Electronics Co.,Ltd

Part # HMD4M1Z1-6
Description  4Mbit(4Mx1bit) Fast Page Mode, 1K Refresh, 20Pin ZIP, 5V Design
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Manufacturer  HANBIT [Hanbit Electronics Co.,Ltd]
Direct Link  http://www.hbe.co.kr
Logo HANBIT - Hanbit Electronics Co.,Ltd

HMD4M1Z1-6 Datasheet(HTML) 4 Page - Hanbit Electronics Co.,Ltd

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HANBit
HMD4M1Z1
URL:www.hbe.co.kr
HANBit Electronics Co.,Ltd.
REV.1.0 (August. 2002)
4
tRCH
Read Command Hold Time to /CAS
0
0
ns
8
tRRH
Read Command Hold Time to /RAS
0
0
ns
8
tWCH
Write Command Hold Time
10
10
ns
tWP
Write Command Pulse Width
10
10
ns
tRWL
Write Command to /RAS Lead Time
15
15
ns
tCWL
Write Command to /CAS Lead Time
13
15
ns
tDS
Data-in Setup Time
0
0
ns
9
tDH
Data-in Hold Time
10
10
ns
9
tREF
Refresh Period (1024 Cycle)
16
16
ms
twcs
Write Command Setup Time
0
0
ms
7
tCWD
/CAS to /WE delay time
15
15
ms
7,13
tRWD
/RAS to /WE delay time
50
60
ns
7
tAWD
Column Address to /WE delay time
25
30
ns
7
tCPWD
/CAS precharge to /WE delay time
30
35
ns
7
tCSR
/CAS Setup Time
(/CAS-before-/RAS Refresh Cycle)
10
10
ns
15
tCHR
/CAS Hold Time
(/CAS-before-/RAS Refresh Cycle)
10
10
ns
16
tRPC
/RAS Precharge to /CAS Hold Time
5
5
ns
tCPA
Access Time from /CAS Precharge
30
35
ns
3
tPC
Fast Page Mode Cycle Time
35
40
ns
tCP
Fast Page Mode /RAS Precharge Time
10
10
ns
12
tRASP
Fast Page Mode /CAS Pulse Time
50
200K
60
200K
ns
tRHCP
/RAS
Hold
Time
time
from
/CAS
Precharge
30
35
ns
tRASS
/RAS Pulse Width(CBR self refresh)
100
100
us
tPRS
/RAS Precharge Time(CBR self refresh)
90
110
ns
tCHS
/CAS Hold Time(CBR self refresh)
-50
-50
ns
Note:
1. An initial pause of 200us is required after power-up followed by any 8 /RAS-only refresh or /CAS-before-/RAS refresh
cycles
before proper device operation is achieved.
2. Input voltage levels are VIH / VIL. VIH(min) and VIL(max) are reference levels for measuring timing of input signals.
Also, transition times are measured between . VIH and VIL are assumed to be 5ns for all inputs.
3. Measured with a load circuit equivalent to 2TTL loads and 100pF.
4. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only,
if tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC .
5. Assumes that tRCD <= tRCD (max).
6. This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH /
VOL .


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