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24LLC02 Datasheet(PDF) 6 Page - Ceramate Technical |
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24LLC02 Datasheet(HTML) 6 Page - Ceramate Technical |
6 / 19 page 24LLC02 2K-Bits Serial EEPROM For Low Power * All specs and applications shown above subject to change without prior notice. 1F-5 NO.66 SEC.2 NAN-KAN RD ., LUCHU , TAOYUAN, TAIWAN Email: server@ceramate.com.tw Tel:886-3-3214525 Http: www.ceramate.com.tw Fax:886-3-3521052 Page 6 of 19 Rev 1.0 Dec. 26, 2001 I 2C-BUS PROTOCOLS Here are several rules for I 2C-bus transfers: — A new data transfer can be initiated only when the bus is currently not busy. — MSB is always transferred first in transmitting data. — During a data transfer, the data line (SDA) must remain stable whenever the clock line (SCL) is High. The I 2C-bus interface supports the following communication protocols: • Bus not busy : The SDA and the SCL lines remain High level when the bus is not active. • Start condition : Start condition is initiated by a High-to-Low transition of the SDA line while SCL remains High level. All bus commands must be preceded by a start condition. • Stop condition : A stop condition is initiated by a Low-to-High transition of the SDA line while SCL remains High level. All bus operations must be completed by a stop condition (see Figure 1-7). SCL SDA Start Condition Data or ACK Valid Data Change Stop Condition Figure 1-7. Data Transmission Sequence • Data valid : Following a start condition, the data becomes valid if the data line remains stable for the duration of the High period of SCL. New data must be put onto the bus while SCL is Low. Bus timing is one clock pulse per data bit. The number of data bytes to be transferred is determined by the master device. The total number of bytes that can be transferred in one operation is theoretically unlimited. • ACK (Acknowledge) : An ACK signal indicates that a data transfer is completed successfully. The transmitter (the master or the slave) releases the bus after transmitting eight bits. During the 9th clock, which the master generates, the receiver pulls the SDA line low to acknowledge that it successfully received the eight bits of data (see Figure 1-8). But the slave does not send an ACK if an internal write cycle is still in progress. In data read operations, the slave releases the SDA line after transmitting 8 bits of data and then monitors the line for an ACK signal during the 9th clock period. If an ACK is detected, the slave will continue to transmit data. If an ACK is not detected, the slave terminates data transmission and waits for a stop condition to be issued by the master before returning to its stand-by mode. |
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