HMD4M36M9EG-5 datasheet(4/7 Pages) HANBIT

Part #	HMD4M36M9EG-5

Description	16Mbyte(4Mx36) 72-pin SIMM, EDO with Parity Mode, 2K/4K Ref. 5V

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Manufacturer	HANBIT [Hanbit Electronics Co.,Ltd]

Direct Link	http://www.hbe.co.kr

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4 / 7 page

HANBit

HMD4M36M9EG, HMD4M36M9EA

URL:www.hbe.co.kr

HANBit Electronics Co.,Ltd.

REV. 1.0. (August. 2002)

- 4 -

ICC6 : /CAS-Before-/RAS Refresh Current * (/RAS and /CAS cycling @tRC=min )

IIL : Input Leakage Current (Any input 0V ≤ VIN ≤ 6.5V, all other pins not under test = 0V)

IOL : Output Leakage Current (Data out is disabled, 0V ≤ VOUT ≤ 5.5V

VOH : Output High Voltage Level (IOH= -5mA )

VOL : Output Low Voltage Level (IOL = 4.2mA )

* NOTE: ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the

output open. ICC is specified as an average current. In ICC1 and ICC3, address cad be changed maximum once

while /RAS=VIL. In ICC4, address can be changed maximum once within one page mode cycle.

CAPACITANCE

( TA=25

o

C, Vcc = 5V, f = 1Mz )

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

Input Capacitance (A0-A10)

CIN1

-

65

pF

Input Capacitance (/W)

C IN2

-

80

pF

Input Capacitance (/RAS0)

CIN3

-

50

pF

Input Capacitance (/CAS0-/CAS3)

CIN4

-

40

pF

Input/Output Capacitance (DQ0-31)

CDQ1

-

20

pF

AC CHARACTERISTICS

( 0

o

C

≤ T

A ≤ 70

oC , Vcc = 5V±10%, See notes 1,2.)

-5

-6

STANDARD OPERATION

SYMBOL

MIN

MAX

MIN

MAX

UNIT

Random read or write cycle time

tRC

90

110

ns

Access time from RAS

tRAC

50

60

ns

Access time from CAS

tCAC

13

15

ns

Access time from column address

tAA

25

30

ns

CAS to output in Low-Z

tCLZ

3

ns

Output buffer turn-off delay

tOFF

3

13

3

15

ns

Transition time (rise and fall)

tT

2

50

2

50

ns

/RAS precharge time

tRP

30

40

ns

/RAS pulse width

tRAS

50

10K

60

10K

ns

/RAS hold time

tRSH

13

15

ns

/CAS hold time

tCSH

38

45

ns

/CAS pulse width

tCAS

8

10K

10

10K

ns

/RAS to /CAS delay time

tRCD

20

37

20

45

ns

/RAS to column address delay time

tRAD

15

25

15

30

ns

/CAS to /RAS precharge time

tCRP

5

ns

Row address set-up time

tASR

0

ns

Row address hold time

tRAH

10

ns

Column address set-up time

tASC

0

ns

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