SSTUA32866EC datasheet(6/27 Pages) PHILIPS

Part #	SSTUA32866EC

Description	1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications

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Manufacturer	PHILIPS [NXP Semiconductors]

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6 / 27 page

9397 750 14759

Product data sheet

Rev. 01 — 15 July 2005

6 of 27

Philips Semiconductors

SSTUA32866

1.8 V DDR2-667 conﬁgurable registered buffer with parity

6.2 Pin description

Table 2:

Pin description

Symbol

Type

Description

GND

B3, B4, D3, D4,

F3, F4, H3, H4,

K3, K4, M3, M4,

P3, P4

ground input

ground

VDD

A4, C3, C4, E3,

E4, G3, G4, J3,

J4, L3, L4, N3,

N4, R3, R4, T4

1.8 V nominal

power supply voltage

VREF

A3, T3

0.9 V nominal

input reference voltage

CK

H1

Differential input

positive master clock input

CK

J1

Differential input

negative master clock input

C0

G6

LVCMOS inputs

Conﬁguration control inputs; Register A

or Register B and 1 : 1 mode or

1 : 2 mode select.

C1

G5

RESET

G2

LVCMOS input

Asynchronous reset input (active LOW).

Resets registers and disables VREF data

and clock.

CSR

J2

SSTL_18 input

Chip select inputs (active LOW). Disables

D1 to D25 [2] outputs switching when both

inputs are HIGH.

DCS

H2

D1 to D25

[1]

SSTL_18 input

Data input. Clocked in on the crossing of

the rising edge of CK and the falling edge

of CK.

DODT

[1]

SSTL_18 input

The outputs of this register bit will not be

suspended by the DCS and CSR control.

DCKE

[1]

SSTL_18 input

The outputs of this register bit will not be

suspended by the DCS and CSR control.

PAR_IN

G1

SSTL_18 input

Parity input. Arrives one clock cycle after

the corresponding data input.

Q1 to Q25,

Q2A to Q14A,

Q1B to Q14B

[1]

1.8 V CMOS

outputs

Data outputs that are suspended by the

DCS and CSR control [3].

PPO

A2

1.8 V CMOS

output

Partial parity out. Indicates odd parity of

inputs D1 to D25 [2].

QCS, QCSA,

QCSB

[1]

1.8 V CMOS

output

Data output that will not be suspended by

the DCS and CSR control.

QODT, QODTA,

QODTB

[1]

1.8 V CMOS

output

Data output that will not be suspended by

the DCS and CSR control.

QCKE, QCKEA,

QCKEB

[1]

1.8 V CMOS

output

Data output that will not be suspended by

the DCS and CSR control.

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