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HMD8M32M16G Datasheet(PDF) 5 Page - Hanbit Electronics Co.,Ltd |
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HMD8M32M16G Datasheet(HTML) 5 Page - Hanbit Electronics Co.,Ltd |
5 / 8 page HANBit HMD8M32M16 URL:www.hbe.co.kr HANBit Electronics Co.,Ltd. REV.1.0 (August.2002) 5 Row address set-up time tASR 0 0 ns Row address hold time tRAH 10 10 ns Column address set-up time tASC 0 0 ns Column address hold time tCAH 15 15 ns Column address hold referenced to /RAS tAR 50 55 ns Column Address to /RAS lead time tRAL 30 35 ns Read command set-up time tRCS 0 0 ns Read command hold referenced to /CAS tRCH 0 0 ns Read command hold referenced to /RAS tRRH 0 0 ns Write command hold time tWCH 15 15 ns Write command hold referenced to /RAS tWCR 50 55 ns Write command pulse width tWP 15 15 ns Write command to /RAS lead time tRWL 15 20 ns Write command to /CAS lead time tCWL 15 20 ns Data-in set-up time tDS 0 0 ns Data-in hold time tDH 15 15 ns Data-in hold referenced to /RAS tDHR 50 55 ns Refresh period tREF 16 16 ns Write command set-up time tWCS 0 0 ns /CAS setup time (C-B-R refresh) tCSR 10 10 ns /CAS hold time (C-B-R refresh) tCHR 15 15 ns /RAS precharge to /CAS hold time tRPC 5 5 ns Access time from /CAS precharge tCPA 35 40 ns Fast page mode cycle time tPC 40 45 ns /CAS precharge time (Fast page) tCP 10 10 ns /RAS pulse width (Fast page ) tRASP 60 100K 70 100K ns /W to /RAS precharge time (C-B-R refresh) tWRP 10 10 ns /W to /RAS hold time (C-B-R refresh) tWRH 10 10 ns /CAS precharge(C-B-R counter test) tCPT 20 30 ns NOTES 1.An initial pause of 200 µs is required after power-up followed by any 8 /RAS-only or /CAS-before-/RAS refresh cycles before proper device operation is achieved. 2.VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. 3.Measured with a load equivalent to 1TTL loads and 100pF 4.Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only. If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. 5.Assumes that tRCD ≥ tRCD(max) 6. tAR, tWCR, tDHR are referenced to tRAD(max) 7.This parameter defines the time at which the output achieves the open circuit condition and is not referenced to VOH |
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