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HMN1M8DN-120 Datasheet(PDF) 2 Page - Hanbit Electronics Co.,Ltd |
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HMN1M8DN-120 Datasheet(HTML) 2 Page - Hanbit Electronics Co.,Ltd |
2 / 9 page HANBit HMN1M8DN URL : www.hbe.co.kr 2 HANBit Electronics Co.,Ltd. REV. 0.2 (August, 2002) FUNCTIONAL DESCRIPTION The HMN1M8DN executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by the address inputs(A0-A19) defines which of the 1,048,576 bytes of data is accessed. Valid data will be available to the eight data output drivers within tACC (access time) after the last address input signal is stable. When power is valid, the HMN1M8DN operates as a standard CMOS SRAM. During power-down and power-up cycles, the HMN1M8DN acts as a nonvolatile memory, automatically protecting and preserving the memory contents. The HMN1M8DN is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. /WE must return to the high state for a minimum recovery time (tWR) before another cycle can be initiated. The /OE control signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled (/CE and /OE active) then /WE will disable the outputs in tODW from its falling edge. The HMN1M8DN provides full functional capability for Vcc greater than 4.5 V and write protects by 4.37 V nominal. Power- down/power-up control circuitry constantly monitors the Vcc supply for a power-fail-detect threshold VPFD. When VCC falls below the VPFD threshold, the SRAM automatically write-protects the data. All inputs to the RAM become “don’t care” and all outputs are high impedance. As Vcc falls below approximately 3 V, the power switching circuit connects the lithium energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 3.0 volts, the power switching circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume after Vcc exceeds 4.5 volts. BLOCK DIAGRAM PIN DESCRIPTION A0-A19 : Address Input /CE : Chip Enable VSS : Ground DQ0-DQ7 : Data In / Data Out /WE : Write Enable /OE : Output Enable VCC: Power (+5V) NC : No Connection DQ0-DQ7 A0-A18 /OE /WE /CE CON Power VCC Lithium Cell 2 x 512K x 8 SRAM Block /CE Power – Fail Control A19 |
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