HANBit

HMN5128DV

URL:www.hbe.co.kr

2

HANBit Electronics Co.,Ltd.

Rev.0.0 (FEBRUARY/ 2002)

FUNCTIONAL DESCRIPTION

The HMN5128DV executes a read cycle whenever /WE is inactive(high) and /CE is active(low). The address specified by

When power is valid, the HMN5128DV operates as a standard CMOS SRAM. During power-down and power-up cycles,

the HMN5128DV acts as a nonvolatile memory, automatically protecting and preserving the memory contents.

The HMN5128DV is in the write mode whenever the /WE and /CE signals are in the active (low) state after address inputs

are stable. The later occurring falling edge of /CE or /WE will determine the start of the write cycle. The write cycle is

terminated by the earlier rising edge of /CE or /WE. All address inputs must be kept valid throughout the write cycle. /WE

signal should be kept inactive (high) during write cycles to avoid bus contention. However, if the output bus been enabled

The HMN5128DV provides full functional capability for Vcc greater than 3.0 V and write protects by 2.8 V nominal. Power-

all outputs are high impedance. As Vcc falls below approximately 2.5 V, the power switching circuit connects the lithium

energy soure to RAM to retain data. During power-up, when Vcc rises above approximately 2.5 volts, the power switching

circuit connects external Vcc to the RAM and disconnects the lithium energy source. Normal RAM operation can resume

after Vcc exceeds 3.0 volts.

BLOCK DIAGRAM

PIN DESCRIPTION

NC : No Connection

/CE : Chip Enable

/WE : Write Enable

/OE : Output Enable

/OE

/WE

Power

Lithium

Cell

512K x 8

SRAM

Block

/CE

Power – Fail

Control