1

PS2013B

10/07/04

Description

PericomSemiconductor’s PI74FCT273Tisa8-bitwideoctaldesigned

with eight edge-triggered D-type flip-flops with individual D inputs

and O outputs. The common buffered Clock (CP) and Master Reset

(MR) load and resets (clear) all flip-flops simultaneously. The

register is fully edge-triggered. The D input state, one setup time

before the LOW-to-HIGH clock transition, is transferred to the

corresponding flip-flop's O output. All outputs will be forced LOW

independently of Clock or Data inputs by a LOW voltage level on

the MR input.

Device models available upon request.

Fast CMOS Octal D Flip-Flop

with Master Reset

Block Diagram

Inputs

Outputs

Mode

MR

CP

Reset (Clear) L

X

X

L

Load "1"

H

↑

hH

Load "0"

H

↑

lL

Pin Name

Description

MR

Master Reset (Active LOW)

CP

Clock Pulse Input

(Active Rising Edge)

Data Inputs

Data Outputs

GND

Ground

Power

PinDescription

PinConfiguration

1. H = High Voltage Level

h = High Voltage Level one setup time

prior to the LOW-to-HIGH Clock

transition

L = Low Voltage Level

l = LOW Voltage Level one setup time

prior to the LOW-to-HIGH Clock

Transition

X = Don’t Care

↑ = LOW-to-HIGH Clock Transition

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PI74FCT273T

Features

• Pin compatible with bipolar FAST™ Series at a higher speed

and lower power consumption

• TTL input and output levels

• Low ground bounce outputs

• Extremely low static power

• Hysteresis on all inputs

• Industrial operating temperature range: –40°C to +85°C

• Packaging:

– 20-pin 173-mil wide plastic TSSOP (L)

– 20-pin 150-mil wide plastic QSOP (Q)

– 20-pin 300-mil wide plastic SOIC (S)

D

CP

CP

MR

Q

D

CP

Q

D

CP

Q

D

CP

Q

D

CP

Q

D

CP

Q

D

CP

Q

D

CP

Q

1

2

3

4

5

6

7

8

9

10

20

19

18

17

16

15

14

13

12

11

MR

GND

Vcc

CP

20-Pin

L20

Q20

S20