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XR16L570 Datasheet(PDF) 7 Page - Exar Corporation |
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XR16L570 Datasheet(HTML) 7 Page - Exar Corporation |
7 / 46 page xr XR16L570 REV. 1.0.0 SMALLEST 1.62V TO 5.5V UART WITH 16-BYTE FIFO AND POWERSAVE 7 2.2 5-Volt Tolerant Inputs The L570 can accept up to 5V inputs when operating at 3.3V, 2.5V or 1.8V. But note that if the L570 is operating at 2.5V or below, its VOH may not be high enough to meet the requirements of the VIH of a CPU or a serial transceiver that is operating at 5V. Note that the XTAL1 (CLK) pin is not 5V tolerant. 2.3 Device Hardware Reset The RESET input resets the internal registers and the serial interface outputs in both channels to their default state (see Table 11). An active pulse of longer than 40 ns duration will be required to activate the reset function in the device. 2.4 Device Identification and Revision The XR16L570 provides a Device Identification code and a Device Revision code. To read the identification code from the part, it is required to set the baud rate generator registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x01 to indicate XR16L570 and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means revision A. 2.5 Internal Registers The L570 has a set of enhanced registers for control, monitoring and data loading and unloading. The configuration register set is compatible to those already available in the standard 16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers (ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status and control registers (MSR/ MCR), programmable data rate (clock) divisor registers (DLL/DLM), and an user accessible Scratchpad register (SPR). Beyond the general 16C550 features and capabilities, the L570 offers enhanced feature registers (EFR, Xon1, Xoff 1, Xon1 and Xoff2) that provide automatic RTS and CTS hardware flow control and Xon/Xoff software flow control. All the register functions are discussed in full detail later in “Section 3.0, UART INTERNAL REGISTERS” on page 19. 2.6 DMA Mode The DMA Mode (a legacy term) refers to data block transfer operation. The DMA mode affects the state of the RXRDY# and TXRDY# output pins available in the original 16C550. These pins are not available in the XR16L570. The DMA Enable bit (FCR bit-3) does not have any function in this device and can be a ’0’ or a ’1’. 2.7 INT Output The interrupt output changes according to the operating mode and enhanced features setup. Table 1 and Table 2 below summarize the operating behavior for the transmitter and receiver. Also see Figures 18 through 21. TABLE 1: INT PIN OPERATION FOR TRANSMITTER FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) INT Pin 0 = one byte in THR 1 = THR empty 0 = FIFO above trigger level 1 = FIFO below trigger level or FIFO empty TABLE 2: INT PIN OPERATION FOR RECEIVER FCR BIT-0 = 0 (FIFO DISABLED) FCR BIT-0 = 1 (FIFO ENABLED) INT Pin 0 = no data 1 = 1 byte 0 = FIFO below trigger level 1 = FIFO above trigger level |
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