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HX6408XQRM Datasheet(PDF) 2 Page - Honeywell Solid State Electronics Center |
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HX6408XQRM Datasheet(HTML) 2 Page - Honeywell Solid State Electronics Center |
2 / 11 page HX6408 Advanced Information 2 www.honeywell.com FUNCTIONAL DIAGRAM 36 LEAD FLAT PACK PINOUT SIGNAL DEFINITIONS A: 0-18 Address input pins, which select a particular eight-bit word within the memory array. DQ: 0-7 Bidirectional data pins, which serve as data outputs during a read operation and as data inputs during a write operation. NCS Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state. If this signal is not used it must be connected to VSS. NWE Negative write enable, when at a low level activates a write operation and holds the data output drivers in a high impedance state. When at a high level NWE allows normal read operation. NOE Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a low level, the data output driver state is defined by NCS, NWE and NSL. This signal is asynchronous. NSL Not sleep, when at a high level allows normal operation. When at a low level NSL forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers except the NCS and NOE input buffers. If this signal is not used it must be connected to VDD. This signal is asynchronous. The HX6408 may be ordered without the sleep mode option and pin 36 is then a NC. All controls must be enabled for signal to pass. # = number of buffers, Default = 1 Signal Signal 1 = enabled # Memory Array DQ(0:7) WE • CS NOE NCS NSL NWE An NWE • CS A0 1 A1 2 A2 3 A3 4 A4 5 NCS 6 D0 7 D1 8 VDD 9 VSS 10 D2 11 D3 12 NWE 13 A5 14 A6 15 A7 16 A8 17 A9 18 36 (NSL) 35 A18 34 A17 33 A16 32 A15 31 NOE 30 D4 29 D5 28 VSS 27 VDD 26 D6 25 D7 24 A14 23 A13 22 A12 21 A11 20 A10 19 NAS HX6408 Top View |
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