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XRK69772IR Datasheet(PDF) 9 Page - Exar Corporation |
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XRK69772IR Datasheet(HTML) 9 Page - Exar Corporation |
9 / 12 page PRELIMINARY XRK69772 9 REV. P1.0.0 1:12 LVCMOS PLL CLOCK GENERATOR FIGURE 6. OUTPUT-TO-OUTPUT SKEW tSK(O) FIGURE 7. PROPOGATION DELAY (t(Ø), STATIC PHASE OFFSET) TEST REFERENCE FIGURE 8. OUTPUT DUTY CYCLE (DC) FIGURE 9. I/O JITTER The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device. V CC V CC÷2 GND V CC V CC÷2 GND t SK(O) FB_IN t (Ø) CCLKx V CC V CC÷2 GND V CC V CC÷2 GND tp T 0 DC=t P/T0 x 100% The time from the PLL controlled edge to the non controlled edge, divided by the time between PLL controlled edges, expressed as a percentage V CC V CC÷2 GND FB_IN CCLKx T JIT(I/O) = |T0-T1mean | The deviation in t 0 for a controlled edge with respect to a t0 mean in a random sample of cycles |
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