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XRK69773CR Datasheet(PDF) 8 Page - Exar Corporation |
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XRK69773CR Datasheet(HTML) 8 Page - Exar Corporation |
8 / 12 page XRK69773 PRELIMINARY 8 1:12 LVCMOS PLL CLOCK GENERATOR REV. P1.0.0 3.0 QSYNC TIMING XRK69773 INDIVIDUAL OUTPUT DISABLE (STOP CLOCK) CIRCUITRY The user can write to the serial input register through the STOP_DATA input by supplying a logic ’0’ start bit followed serially by 12 NRZ disable/enable bits. The period of each STOP_DATA bit equals the period of the free-running STOP_CLK signal. The STOP_DATA serial transmission should be timed so the XRK69773 can sample each STOP_DATA bit with the rising edge of the free-running STOP_CLK signal. A logic "0" to any stop bit location will disable the corresponding device output while a logic "1" will enable. All outputs are by default, enabled. FIGURE 4. QSYNC TIMING DIAGRAM FIGURE 5. STOP CLOCK CIRCUIT PROGRAMMING f VCO 12345 6789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 2 5 2 6 2 7 QA QC QSYNC 1:1 Mode 2:1 Mode QA QC QSYNC QA(/4) QSYNC 3:1 Mode 3:2 Mode QC(/6) QC(/2) QSYNC QA(/6) 2 8 2 9 3 0 3 1 QA(/6) QSYNC QC(/8) QC(/2) QSYNC QA(/8) 4:1 Mode 4:3 Mode QA(/12) QSYNC QC(/2) 6:1 Mode START QA0 QA1 QA2 QA3 QB0 QB1 QB2 QB3 QC1 QC2 QC3 QSYNC STOP_CLK STOP_DATA |
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