XR16C854DIV datasheet(1/54 Pages) EXAR

Part #	XR16C854DIV

Description	2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

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Manufacturer	EXAR [Exar Corporation]

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Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

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XR16C854/854D

2.97V TO 5.5V QUAD UART WITH 128-BYTE FIFO

AUGUST 2005

REV. 3.0.1

GENERAL DESCRIPTION

The XR16C854/854D1 (854) is an enhanced quad

Universal Asynchronous Receiver and Transmitter

(UART) each with 128 bytes of transmit and receive

FIFOs, transmit and receive FIFO counters and

trigger levels, automatic hardware and software flow

control, and data rates of up to 2 Mbps. Each UART

has a set of registers that provide the user with

operating

status

and

control,

receiver

error

indications, and modem serial interface controls.

System interrupts may be tailored to meet design

requirements. An internal loopback capability allows

onboard diagnostics. The 854 is available in 64-pin

LQFP, 68-pin PLCC and 100-pin QFP packages. The

64-pin package only offers the 16 mode interface, but

the 68 and 100 pin packages offer an additional 68

mode interface which allows easy integration with

Motorola processors.

The XR16C854CV (64 pin)

offers three state interrupt outputs while the

XR16C854DV provides continuous interrupt outputs.

The 100 pin package provides additional FIFO status

outputs (TXRDY# and RXRDY# A-D), separate

infrared transmit data outputs (IRTX A-D) and

channel C external clock input (CHCCLK).

The

XR16C854/854D is compatible with the industry

standard ST16C554/554D and ST16C654/654D.

NOTE: 1 Covered by U.S. Patent #5,649,122 and #5,949,787.

FEATURES

Added feature in devices with top mark date code of

"F2 YYWW" and newer:

■ 5 volt tolerant inputs

• 2.97 to 5.5 Volt Operation

• Pin-to-pin compatible with the industry standard

ST16C554 and ST16C654 and TI’s TL16C554N

and TL16C754BFN

• Intel or Motorola Data Bus Interface select

• Four independent UART channels

■ Register Set Compatible to 16C550

■ Data rates of up to 2 Mbps

■ Transmit and Receive FIFOs of 128 bytes

■ Programmable TX and RX FIFO Trigger Levels

■ Transmit and Receive FIFO Level Counters

■ Automatic Hardware (RTS/CTS) Flow Control

■ Selectable Auto RTS Flow Control Hysteresis

■ Automatic Software (Xon/Xoff) Flow Control

■ Wireless Infrared (IrDA 1.0) Encoder/Decoder

• Sleep Mode (200 uA typical)

• Crystal oscillator or external clock input

APPLICATIONS

• Portable Appliances

• Telecommunication Network Routers

• Ethernet Network Routers

• Cellular Data Devices

• Factory Automation and Process Controls

FIGURE 1. XR16C854 BLOCK DIAGRAM

XTAL1

XTAL2

Crystal Osc/Buffer

Data Bus

Interface

UART Channel A

128 Byte TX FIFO

128 Byte RX FIFO

BRG

IR

ENDEC

TX & RX

UART

Regs

2.97V to 5.5V VCC

GND

854 BLK

TXB, RXB, IRTXB, DTRB#,

DSRB#, RTSB#, CTSB#,

CDB#, RIB#, OP2B#

UART Channel B

(same as Channel A)

A2:A0

D7:D0

CSA#

16/68#

CSB#

INTA

INTB

IOW#

IOR#

Reset

INTSEL

CHCCLK

TXRDY# A-D

RXRDY# A-D

UART Channel C

(same as Channel A)

TXA, RXA, IRTXA, DTRA#,

DSRA#, RTSA#, CTSA#,

CDA#, RIA#, OP2A#

TXC, RXC, IRTXC, DTRC#,

DSRC#, RTSC#, CTSC#,

CDC#, RIC#, OP2C#

UART Channel D

(same as Channel A)

TXD, RXD, IRTXD, DTRD#,

DSRD#, RTSD#, CTSD#,

CDD#, RID#, OP2D#

CSC#

CSD#

INTC

INTD

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