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XRT72L56 Datasheet(PDF) 10 Page - Exar Corporation

Part # XRT72L56
Description  SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT72L56 Datasheet(HTML) 10 Page - Exar Corporation

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SIX CHANNEL DS3/E3 FRAMER IC WITH HDLC CONTROLLER
REV. P1.1.2
PRELIMINARY
VIII
202
II/O CONTROL REGISTER (ADDRESS = 0X01) ......................................................................................... 203
TABLE 36: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (TXLINECLK INV) WITHIN THE I/O CONTROL
REGISTER AND THE TXLINECLK CLOCK EDGE THAT TXPOS AND TXNEG ARE UPDATED ON ..................... 203
Figure 75. Illustration on how the Receive DS3 Framer (within the XRT72L56 Framer IC) being interfaced
to theXRT73L03 LIU, while the Framer is operating in Bipolar Mode (one channel shown) ............... 203
Figure 76. Illustration of AMI Line Code ............................................................................................. 204
Figure 77. Illustration of two examples of B3ZS Decoding ................................................................. 205
II/O CONTROL REGISTER (ADDRESS = 0X01) ......................................................................................... 205
TABLE 37: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (RXLINECLK INV) OF THE I/O CONTROL REG-
ISTER
, AND THE SAMPLING EDGE OF THE RXLINECLK SIGNAL ................................................................... 205
Figure 78. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and
RxNEG are to be sampled on the rising edge of RxLineClk ................................................................ 206
Figure 79. Waveform/Timing Relationship between RxLineClk, RxPOS and RxNEG - When RxPOS and
RxNEG are to be sampled on the falling edge of RxLineClk ............................................................... 206
4.3.2 The Receive DS3 Framer Block ............................................................................................................ 206
Figure 80. A Simple Illustration of the Receive DS3 Framer Block and the Associated Paths to the Other
Functional Blocks ................................................................................................................................ 207
Figure 81. The State Machine Diagram for the Receive DS3 Framer block's Frame Acquisition/Mainte-
nance Algorithm ................................................................................................................................... 208
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 209
TABLE 38: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 2 (FRAMING ON PARITY) WITHIN THE RX DS3
CONFIGURATION AND STATUS REGISTER, AND THE RESULTING FRAMING ACQUISITION CRITERIA .............. 209
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 209
TABLE 39: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 1 (F-SYNC ALGO) WITHIN THE RX DS3 CONFIG-
URATION AND
STATUS REGISTER, AND THE RESULTING F-BIT OOF DECLARATION CRITERIA USED BY THE RECEIVE
DS3 FRAMER BLOCK ............................................................................................................................. 210
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 210
TABLE 40: THE RELATIONSHIP BETWEEN THE CONTENTS OF BIT 0 (M-SYNC ALGO) WITHIN THE RX DS3 CONFIG-
URATION AND
STATUS REGISTER, AND THE RESULTING M-BIT OOF DECLARATION CRITERIA USED BY THE RE-
CEIVE
DS3 FRAMER BLOCK .................................................................................................................... 210
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 210
I/O CONTROL REGISTER (ADDRESS = 0X01) .......................................................................................... 211
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X52) ................................. 211
PMON FRAMING BIT ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X53) .................................. 211
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 212
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 212
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 213
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 213
RX DS3 CONFIGURATION AND STATUS REGISTER, (ADDRESS = 0X10) ................................................... 213
RX DS3 STATUS REGISTER (ADDRESS = 0X11) ..................................................................................... 214
RX DS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) .................................................................... 214
RXDS3 STATUS REGISTER (ADDRESS = 0X11) ...................................................................................... 215
RXDS3 INTERRUPT STATUS REGISTER (ADDRESS = 0X13) ..................................................................... 215
PMON PARITY ERROR EVENT COUNT REGISTER - MSB (ADDRESS = 0X54) .......................................... 215
PMON PARITY ERROR EVENT COUNT REGISTER - LSB (ADDRESS = 0X55) ........................................... 215
Figure 82. A Simple Illustration of the Locations of the Source, Mid-Network and Sink Terminal Equipment
(for CP-Bit Processing) ........................................................................................................................ 216
Figure 83. Illustration of the Presumed Configuration of the Mid-Network Terminal Equipment ........ 217
4.3.3 The Receive HDLC Controller Block ..................................................................................................... 218
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ............................................ 219
RX DS3 FEAC REGISTER (ADDRESS = 0X16) ....................................................................................... 219
RX DS3 FEAC INTERRUPT ENABLE/STATUS REGISTER (ADDRESS = 0X17) ............................................ 219
Figure 84. Flow Diagram depicting how the Receive FEAC Processor Functions ............................. 220
Figure 85. LAPD Message Frame Format .......................................................................................... 221


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