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HX6408XVFM Datasheet(PDF) 3 Page - Honeywell Solid State Electronics Center |
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HX6408XVFM Datasheet(HTML) 3 Page - Honeywell Solid State Electronics Center |
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3 / 11 page  HX6408 Advanced Information 3 www.honeywell.com TRUTH TABLE NCS NSL NWE NOE Mode DQ L H H L Read Data Out L H L X Write Data In H X X X Deselected High Z X L X X Sleep High Z X: VI = VIH or VIL, NOE=H: High Z output state maintained for NCS=X, NWE=X RADIATION Total Ionizing Radiation Dose The SRAM will meet all stated functional and electrical specifications over the entire operating temperature range after the specified total ionizing radiation dose. All electrical and timing performance parameters will remain within specifications. Total dose hardness is assured by wafer level testing of process monitor transistors and RAM product using 10 KeV X-ray. Transistor gate threshold shift correlations have been made between 10 KeV X-rays applied at a dose rate of 1x10 5 rad(SiO2)/min at T= 25°C and gamma rays (Cobalt 60 source) to ensure that wafer level X-ray testing is consistent with standard military radiation test environments. Transient Pulse Ionizing Radiation The SRAM is capable of writing, reading, and retaining stored data during and after exposure to a transient ionizing radiation pulse, up to the specified transient dose rate upset specification, when applied under recommended operating conditions. It is recommended to provide external power supply decoupling capacitors to maintain VDD voltage levels during transient events. The SRAM will meet any functional or electrical specification after exposure to a radiation pulse up to the transient dose rate survivability specification, when applied under recommended operating conditions. Note that the current conducted during the pulse by the RAM inputs, outputs, and power supply may significantly exceed the normal operating levels. The application design must accommodate these effects. Neutron Radiation The SRAM will meet any functional or timing specification after exposure to the specified neutron fluence under recommended operating or storage conditions. This assumes an equivalent neutron energy of 1 MeV. Soft Error Rate The SRAM is capable of meeting the specified Soft Error Rate (SER), under recommended operating conditions. This hardness level is defined by the Adams 90% worst case cosmic ray environment for geosynchronous orbits. Latchup The SRAM will not latch up due to any of the above radiation exposure conditions when applied under recommended operating conditions. Fabrication with the SOI substrate material provides oxide isolation between adjacent PMOS and NMOS transistors and eliminates any potential SCR latchup structures. Sufficient transistor body tie connections to the p- and n-channel substrates are made to ensure no source/drain snapback occurs. |
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