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XRT73L02M Datasheet(PDF) 2 Page - Exar Corporation

Part # XRT73L02M
Description  TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT73L02M Datasheet(HTML) 2 Page - Exar Corporation

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XRT73L02M
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TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT
2
TRANSMIT INTERFACE CHARACTERISTICS
• Accepts either Single-Rail or Dual-Rail data from
Terminal Equipment and generates a bipolar signal
to the line
• Integrated Pulse Shaping Circuit.
• Built-in B3ZS/HDB3 Encoder (which can be dis-
abled).
• Accepts Transmit Clock with duty cycle of 30%-
70%.
• Generates pulses that comply with the ITU-T G.703
pulse template for E3 applications.
• Generates pulses that comply with the DSX-3 pulse
template, as specified in Bellcore GR-499-CORE
and ANSI T1.102_1993.
• Generates pulses that comply with the STSX-1
pulse template, as specified in Bellcore GR-253-
CORE.
• Transmitter can be turned off in order to support
redundancy designs.
RECEIVE INTERFACE CHARACTERISTICS
• Integrated Adaptive Receive Equalization for opti-
mal Clock and Data Recovery.
• Declares and Clears the LOS defect per ITU-T
G.775 requirements for E3 and DS3 applications.
• Meets Jitter Tolerance Requirements, as specified
in ITU-T G.823_1993 for E3 Applications.
• Meets Jitter Tolerance Requirements, as specified
in Bellcore GR-499-CORE for DS3 Applications.
• Declares Loss of Signal (LOS) and Loss of Lock
(LOL) Alarms.
• Built-in B3ZS/HDB3 Decoder (which can be dis-
abled).
• Recovered Data can be muted while the LOS Con-
dition is declared.
• Outputs either Single-Rail or Dual-Rail data to the
Terminal Equipment.
FIGURE 1. BLOCK DIAGRAM OF THE XRT 73L02M
HOST/HW
STS-1/DS3
E3
REQEN
RTIP
RRING
SR/DR
XRT75L03
RLB
RLOS
TPOS
TNEG
TxClk
TAOS
TxLEV
TxON
Note: Serial Processor Interface input pins are shared by in "Host" Mode and redefined in the "Hardware" Mode.
Device
Monitor
MTIP
MRING
DMO
Timing
Control
TTIP
TRING
Tx
Pulse
Shaping
HDB3/
B3ZS
Encoder
RLOL
RxON
RxClkINV
RxClk
RPOS
RNEG/
LCV
Tx
Control
MUX
Line
Driver
LLB
Invert
Remote
LoopBack
HDB3/
B3ZS
Decoder
MUX
AGC/
Equalizer
Peak Detector
LOS
Detector
Slicer
Serial
Processor
Interface
Local
LoopBack
Clock & Data
Recovery
Clock
Synthesizer
E3Clk,DS3Clk,
STS-1Clk
RESET
CS
SClk
INT
SDO
SDI
CLK_OUT


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