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XRT73L02MIV Datasheet(PDF) 5 Page - Exar Corporation |
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XRT73L02MIV Datasheet(HTML) 5 Page - Exar Corporation |
5 / 46 page xr XRT73L02M TWO CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT REV. 1.0.0 V Figure 17. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 32 Figure 18. Interference Margin Test Set up for E3. ........................................................................................ 32 TABLE 9: INTERFERENCE MARGIN TEST RESULTS .............................................................................................. 32 5.0.2 Clock and Data Recovery: ................................................................................................................. 33 5.0.3 B3ZS/HDB3 Decoder: ........................................................................................................................ 33 5.0.4 LOS (Loss of Signal) Detector: ......................................................................................................... 34 DISABLING ALOS/DLOS DETECTION: ......................................................................................................... 34 TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) ................................................................... 34 Figure 19. Loss Of Signal Definition for E3 as per ITU-T G.775 .................................................................... 35 Figure 20. Loss of Signal Definition for E3 as per ITU-T G.775. .................................................................... 35 6.0 Jitter: ................................................................................................................................................. 36 6.0.1 Jitter Tolerance - Receiver: ............................................................................................................... 36 Figure 21. Jitter Tolerance Measurements ..................................................................................................... 36 Figure 22. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 37 Figure 23. Input Jitter Tolerance for E3 ......................................................................................................... 37 6.0.2 Jitter Transfer - Receiver/Transmitter: ............................................................................................. 38 TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ..................................... 38 TABLE 12: JITTER TRANSFER SPECIFICATION/REFERENCES ............................................................................... 38 TABLE 13: JITTER TRANSFER PASS MASKS ....................................................................................................... 39 Figure 24. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 39 6.1.1 Jitter Generation: ............................................................................................................................... 40 7.0 Serial Host interface: ....................................................................................................................... 40 TABLE 14: FUNCTIONS OF SHARED PINS ............................................................................................................ 40 TABLE 15: REGISTER MAP AND BIT NAMES ....................................................................................................... 40 TABLE 16: REGISTER MAP DESCRIPTION - GLOBAL ............................................................................................ 41 TABLE 17: REGISTER MAP AND BIT NAMES - CHANNEL 0 REGISTERS ................................................................. 42 TABLE 18: REGISTER MAP AND BIT NAMES - CHANNEL 1 REGISTERS ................................................................. 42 TABLE 20: REGISTER MAP DESCRIPTION ........................................................................................................... 43 8.0 Diagnostic Features: ........................................................................................................................ 47 8.1 PRBS GENERATOR AND DETECTOR: ................................................................................................................ 47 8.2 LOOPBACKS: ............................................................................................................................................... 48 8.2.1 ANALOG LOOPBACK: ....................................................................................................................... 48 Figure 25. PRBS MODE ................................................................................................................................. 48 8.2.2 DIGITAL LOOPBACK: ........................................................................................................................ 49 Figure 26. Analog Loopback ........................................................................................................................... 49 8.2.3 REMOTE LOOPBACK: ....................................................................................................................... 50 Figure 27. Digital Loopback ............................................................................................................................ 50 8.3 TRANSMIT ALL ONES (TAOS): ................................................................................................................... 51 Figure 28. Remote Loopback ......................................................................................................................... 51 Figure 29. Transmit All Ones (TAOS) ............................................................................................................. 51 APPENDIX ......................................................................................................................... 52 Figure 30. EVALUATION BOARD SCHEMATICS ......................................................................................... 52 Figure 31. Evaluation Board Schematics ....................................................................................................... 53 ORDERING INFORMATION ................................................................................................................ 54 PACKAGE DIMENSIONS - 14X20 MM, 100PIN PACKAGE ................................................................................ 54 REVISIONS ................................................................................................................................................. 55 |
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