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XRT73L03B Datasheet(PDF) 1 Page - Exar Corporation |
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XRT73L03B Datasheet(HTML) 1 Page - Exar Corporation |
1 / 61 page Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com XRT73L03B 3 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT OCTOBER 2003 REV. 1.0.1 GENERAL DESCRIPTION The XRT73L03B, 3-Channel, DS3/E3/STS-1 Line In- terface Unit is a low power CMOS version of the XRT73L03A and consists of three independent line transmitters and receivers integrated on a single chip designed for DS3, E3 or SONET STS-1 applications. Each channel of the XRT73L03B can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET STS-1 (51.84 Mbps) rates. Each channel can be configured to operate in a mode/data rate that is independent of the other channels. In the transmit direction, each channel encodes input data to either B3ZS (DS3/STS-1) or HDB3 (E3) for- mat and converts the data into the appropriate pulse shapes for transmission over coaxial cable via a 1:1 transformer. In the receive direction, the XRT73L03B performs equalization on incoming signals, performs Clock Re- covery, decodes data from either B3ZS or HDB3 for- mat, converts the receive data into TTL/CMOS for- mat, checks for LOS or LOL conditions and detects and declares the occurrence of Line Code Violations. FEATURES • Incorporates an improved Timing Recovery circuit and is pin and functional compatible to XRT73L03A • Meets E3/DS3/STS-1 Jitter Tolerance Require- ments • Contains a 4-Wire Microprocessor Serial Interface • Full Loop-Back Capability • Transmit and Receive Power Down Modes • Full Redundancy Support • Uses Minimum External components • Single +3.3V Power Supply • Low power CMOS design • 5V tolerant I/O • -40°C to +85°C Operating Temperature Range • Available in a 120 pin LQFP package APPLICATIONS • Digital Cross Connect Systems • CSU/DSU Equipment • Routers • Fiber Optic Terminals • Multiplexers • ATM Switches FIGURE 1. XRT73L03B BLOCK DIAGRAM ENDECDIS RLOS_(n) LLB_(n) RLB_(n) TAOS_(n) TPData_(n) TNData_(n) TxClk_(n) TxLEV_(n) TxOFF_(n) Channel 2 - (n) = 2 AGC/ Equalizer Serial Processor Interface Peak Detector LOS Detector Slicer Clock Recovery Data Recovery Invert Loop MUX HDB3/ B3ZS Decoder LOSTHR_(n) SDI SDO SClk CS REGR RTIP_(n) RRing_(n) REQEN_(n) Channel 0 - (n) = 0 Channel 1 - (n) = 1 Notes: 1. (n) = 0, 1, or 2 for respective Channels 2. Serial Processor Interface input pins are shared by the three Channels in HOST Mode and redefined in Hardware Mode. Device Monitor MTIP_(n) MRing_(n) DMO_(n) Transmit Logic Duty Cycle Adjust TTIP_(n) TRing_(n) Pulse Shaping HDB3/ B3ZS Encoder E3_(n) STS-1/DS3_(n) Host/(HW) RLOL_(n) EXClk_(n) RxOFF RxClkINV RxClk_(n) RPOS_(n) RNEG_(n) LCV_(n) Tx Control |
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