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XRT73L04AIV Datasheet(PDF) 7 Page - Exar Corporation

Part # XRT73L04AIV
Description  4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT73L04AIV Datasheet(HTML) 7 Page - Exar Corporation

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XRT73L04A
4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT
REV. 2.0.3
IV
Figure 34. A channel operating in the Analog Local Loop-Back Mode ........................................................... 48
4.2 THE DIGITAL LOCAL LOOP-BACK MODE. ......................................................................................... 49
COMMAND REGISTER CR4-(N) ............................................................................................................ 49
Figure 35.The Digital Local Loop-Back path within a given channel .............................................................. 49
COMMAND REGISTER CR4-(N) ............................................................................................................ 49
4.3 THE REMOTE LOOP-BACK MODE ................................................................................................... 50
Figure 36.The Remote Loop-Back path, within a given channel .................................................................... 50
COMMAND REGISTER CR4-(n) ............................................................................................................ 50
4.4 TXOFF FEATURES ......................................................................................................................... 51
COMMAND REGISTER CR1-(N) ............................................................................................................ 51
Table 6:The Relationship Between the TxOFF Input Pin, the TxOFF Bit Field and the State of the Transmitter
51
4.5 THE TRANSMIT DRIVE MONITOR FEATURES .................................................................................... 51
Figure 37.The XRT73L04A employing the Transmit Drive Monitor Features ................................................. 52
4.6 THE TAOS (TRANSMIT ALL ONES) FEATURE ................................................................................. 52
5.0 THE MICROPROCESSOR SERIAL INTERFACE ................................................................................... 52
5.1 DESCRIPTION OF THE COMMAND REGISTERS .................................................................................. 52
COMMAND REGISTER CR1-(N) ............................................................................................................ 52
Table 7:Hexadecimal Addresses and Bit Formats of XRT73L04A Command Registers ............................... 53
5.2 DESCRIPTION OF BIT-FIELDS FOR EACH COMMAND REGISTER ......................................................... 54
Command Register - CR0-(n) ............................................................................................................ 54
COMMAND REGISTER CR0-(N) ............................................................................................................. 54
COMMAND REGISTER CR1-(N) ............................................................................................................ 55
Command Register CR2-(n) .............................................................................................................. 55
COMMAND REGISTER CR2-(N) ............................................................................................................ 55
COMMAND REGISTER CR3-(N) ............................................................................................................ 56
COMMAND REGISTER CR4-(N) ............................................................................................................ 57
Table 8:Contents of LLB_(n) and RLB_(n) and the Corresponding Loop-Back Mode for Channel(n) ........... 57
5.3 OPERATING THE MICROPROCESSOR SERIAL INTERFACE. ................................................................. 57
Figure 38.Microprocessor Serial Interface Data Structure ............................................................................. 58
Figure 39.Timing Diagram for the Microprocessor Serial Interface ................................................................ 59
ORDERING INFORMATION ..................................................................................................... 60
PACKAGE DIMENSIONS ........................................................................................................ 60
REVISION HISTORY ..................................................................................................................................... 61
REV # ................................................................................................................................................ 61


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