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XRT73LC00A Datasheet(PDF) 1 Page - Exar Corporation |
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XRT73LC00A Datasheet(HTML) 1 Page - Exar Corporation |
1 / 53 page Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com xr PRELIMINARY XRT73LC00A E3/DS3/STS-1 LINE INTERFACE UNIT AUGUST 2004 REV. P1.0.0 GENERAL DESCRIPTION The XRT73LC00A DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L00A and consists of a line transmitter and receiver integrated on a single chip and is designed for DS3, E3 or SO- NET STS-1 applications. XRT73LC00A can be configured to support the E3 (34.368 Mbps), DS3 (44.736 Mbps) or the SONET STS-1 (51.84 Mbps) rates. In the transmit direction, the XRT73LC00A encodes input data to either B3ZS (for DS3/STS-1 applica- tions) or HDB3 (for E3 applications) format and con- verts the data into the appropriate pulse shapes for transmission over coaxial cable via a 1:1 transformer. In the receive direction the XRT73LC00A performs equalization on incoming signals, performs Clock Re- covery, decodes data from either B3ZS or HDB3 for- mat, converts the receive data into TTL/CMOS for- mat, checks for LOS or LOL conditions and detects and declares the occurrence of line code violations. The XRT73LC00A also contains a 4-Wire Micropro- cessor Serial Interface for accessing the on-chip Command registers. FEATURES • Incorporates an improved Timing Recovery circuit and is pin and functional compatible to XRT73L00A • Meets E3/DS3/STS-1 Jitter Tolerance Require- ments • Full Loop-Back Capability • Transmit and Receive Power Down Modes • Full Redundancy Support • Contains a 4-Wire Microprocessor Serial Interface • Uses Minimum External components • Low Power CMOS Design • Single +3.3V Power Supply • 5 V Tolerant pins • -40°C to +85°C Operating Temperature Range • Available in a 44 pin TQFP package APPLICATIONS • Interfaces to E3, DS3 or SONET STS-1 Networks • CSU/DSU Equipment • PCM Test Equipment • Fiber Optic Terminals • Multiplexers FIGURE 1. BLOCK DIAGRAM OF THE XRT73LC00A AGC/ Equalizer Serial Processor Interface Peak D etector LOS D etector Slicer C lock R ecovery Da ta Recovery Invert Loop M UX H DB3/ B 3ZS Decoder LO STH R SD I SD O/(LC V) SC lk CS R EGR ESET R TIP R R ING RE QDIS D evice M onitor M TIP M R ING DM O Tra nsm it Logic Duty Cycle Adjust TTIP TR ING Pulse Shaping HD B3/ B3ZS Encoder E3 STS -1/D S3 Host/(H W ) RLOL EXC LK IC T R CLK INV Tx C ontrol DR /SR RLOS LLB RLB EN DEC DIS TA OS TPD ATA TN D ATA TC lk TXLEV TXO FF RC LK1 RN EG RP OS LC V/(RC LK 2) |
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