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XRT74L73 Datasheet(PDF) 5 Page - Exar Corporation |
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XRT74L73 Datasheet(HTML) 5 Page - Exar Corporation |
5 / 488 page XRT74L73 3 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER PRELIMINARY REV. P1.0.1 6 PIN DESCRIPTION PIN#NAME TYPE DESCRIPTION Microprocessor Interface AB3 AA4 AA1 AA2 Y1 Y2 Y3 A0 A1 A2 A3 A4 A5 A6 I Address Bus Input (Microprocessor Interface): These pins are used to select the on-chip Framer/UNI registers and RAM space for READ/WRITE operations with the “local” microprocessor. V4 NibbleIntf I Nibble Interface Select Input pin: This input pin permits the user to configure the Transmit Payload Data Input Interface and the Receive Payload Data Output Interface blocks to operate in either the "Serial" or the "Nibble-Parallel" Mode. Setting this input pin "high" configures each of these blocks to operate in the Nib- ble-Parallel Mode. In this mode, the "Transmit Payload Data Input Interface" block will accept the "outbound" payload data (from the local terminal equip- ment) in a "nibble-parallel" manner via the "TxNib[2:0]" input pins. Further, the Receive Payload Data Output Interface block will output "inbound" payload data (to the local terminal equipment) in a "nibble-parallel" via the "RxNib[2:0] output pins. Setting this input pin "low" configures each of these blocks to operate in the Serial Mode. In this mode, the Transmit Payload Data Input Interface block will accept the "outbound" payload data (from the local terminal equipment) in a "serial" manner via the "TxSer_n" input pin. Further, the Receive Payload Data Output Interface block will output the "inbound" payload data (to the local termi- nal equipment) in a serial manner, via the "RxSer_n" output pin. NOTE: This input pin is only active if the XRT74L73 device has been configured to operate in the Clear-Channel Framer Mode. AC7 AD6 AE5 AF4 AC5 AD4 AE3 AF2 D0 D1 D2 D3 D4 D5 D6 D7 I/O Bi-Directional Data Bus (Microprocessor Interface Section): These pins function as the Microprocessor Interface bi-directional data bus and is intended to be interfaced to the “local” microprocessor. This pin is inactive if the Microprocessor Interface block is configured to operate over an 8 bit data bus. AE2 ALE_AS I Address Latch Enable/Address Strobe: This input is used to latch the address (present at the Microprocessor Interface Address Bus, A[6:0]) into the Framer/UNI Microprocessor Interface circuitry and to indicate the start of a READ or WRITE cycle. This input is active-"High" in the Intel Mode (MOTO = “Low”) and active-”Low” in the Motorola Mode (MOTO = “High”). AB1 CS I Chip Select Input: This active-”Low” input signal selects the Microprocessor Interface Section of the UNI/Framer and enables Read/Write operations between the “local” micropro- cessor and the UNI/Framer on-chip registers and RAM locations. |
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