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XRT74L74IB Datasheet(PDF) 5 Page - Exar Corporation |
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XRT74L74IB Datasheet(HTML) 5 Page - Exar Corporation |
5 / 498 page XRT74L74 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER PRELIMINARY REV. P1.1.1 III FIGURE 44. TIMING DIAGRAM ILLUSTRATING THE BEHAVIOR OF VARIOUS SIGNALS FROM THE ATM LAYER PROCESSOR AND THE UNI, DURING POLLING. ............................................................................................................................................................................ 184 FIGURE 45. FLOW-CHART OF THE “UNI DEVICE SELECTION AND READ PROCEDURE” FOR THE MULTI-PHY OPERATION........................ 185 FIGURE 46. TIMING DIAGRAM OF THE RECEIVE UTOPIA DATA AND ADDRESS BUS SIGNALS, DURING THE “MULTI-PHY” UNI DEVICE SELECTION AND WRITE OPERATIONS..................................................................................................................................................... 185 XRT74L74 CONFIGURATION .................................................................................................... 190 5.0 DS3 OPERATION OF THE XRT74L74 .............................................................................................. 190 FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 190 5.1 DESCRIPTION OF THE DS3 FRAMES AND ASSOCIATED OVERHEAD BITS ........................................ 190 FIGURE 47. DS3 FRAME FORMAT FOR C-BIT PARITY........................................................................................................................... 190 FIGURE 48. DS3 FRAME FORMAT FOR M13........................................................................................................................................ 191 FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 191 TABLE 32: THE RELATIONSHIP BETWEEN THE CONTENT OF BIT 2, (C-BIT PARITY*/M13) WITHIN THE FRAMER OPERATING MODE REGISTER AND THE RESULTING DS3 FRAMING FORMAT............................................................................................................................... 192 TABLE 33: C-BIT FUNCTIONS FOR THE C-BIT PARITY DS3 FRAME FORMAT .......................................................................................... 192 5.1.1 FRAME SYNCHRONIZATION BITS (APPLIES TO BOTH M13 AND C-BIT PARITY FRAMING FORMATS)....... 192 5.1.2 PERFORMANCE MONITORING/ERROR DETECTION BITS (PARITY)................................................................. 193 5.1.3 ALARM AND SIGNALING-RELATED OVERHEAD BITS ....................................................................................... 193 5.1.4 THE DATA LINK RELATED OVERHEAD BITS....................................................................................................... 194 5.2 THE TRANSMIT SECTION OF THE XRT74L74 (DS3 MODE OPERATION) .............................................. 194 FIGURE 49. A SIMPLE ILLUSTRATION OF THE TRANSMIT SECTION, WITHIN THE XRT74L74, WHEN IT HAS BEEN CONFIGURED TO OPERATE IN THE DS3 MODE......................................................................................................................................................................... 195 5.2.1 THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK ........................................................................... 195 FIGURE 50. A SIMPLE ILLUSTRATION OF THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK ........................................................ 195 TABLE 34: LISTING AND DESCRIPTION OF THE PINS ASSOCIATED WITH THE TRANSMIT PAYLOAD DATA INPUT INTERFACE ....................... 196 FIGURE 51. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK (OF THE XRT74L74) FOR MODE 1(SERIAL/LOOP-TIMING) OPERATION ........................................................................................ 198 FIGURE 52. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK OF THE XRT74L74 AND THE TERMINAL EQUIPMENT (FOR MODE 1 OPERATION) ............................................................................... 199 FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 199 FIGURE 53. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK OF THE XRT74L74 FOR MODE 2 (SERIAL/LOCAL-TIMED/FRAME-SLAVE) OPERATION ................................................................. 200 FIGURE 54. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT74L74 AND THE TERMINAL EQUIPMENT (MODE 2 OPERATION) 201 FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 201 FIGURE 55. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK OF THE XRT74L74 FOR MODE 3 (SERIAL/LOCAL-TIMED/FRAME-MASTER) OPERATION .............................................................. 202 FIGURE 56. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT74L74 AND THE TERMINAL EQUIPMENT (DS3 MODE 3 OPER- ATION ) ................................................................................................................................................................................ 203 FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 204 FIGURE 57. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK OF THE XRT74L74 FOR MODE 4 (NIBBLE-PARALLEL/LOOP-TIMED) OPERATION ......................................................................... 205 FIGURE 58. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT74L74 AND THE TERMINAL EQUIPMENT (MODE 4 OPERATION) 206 FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 206 FIGURE 59. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK OF THE XRT74L74 FOR MODE 5 (NIBBLE-PARALLEL/LOCAL-TIMED/FRAME-SLAVE) OPERATION ................................................. 208 FIGURE 60. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT74L74 AND THE TERMINAL EQUIPMENT (DS3 MODE 5 OPER- ATION ) ................................................................................................................................................................................ 209 FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 209 FIGURE 61. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT PAYLOAD DATA INPUT INTERFACE BLOCK OF THE XRT74L74 FOR MODE 6 (NIBBLE-PARALLEL/LOCAL-TIMED/FRAME-MASTER) OPERATION .............................................. 210 FIGURE 62. BEHAVIOR OF THE TERMINAL INTERFACE SIGNALS BETWEEN THE XRT74L74 AND THE TERMINAL EQUIPMENT (DS3 MODE 6 OPER- ATION ) ................................................................................................................................................................................ 211 FRAMER OPERATING MODE REGISTER (ADDRESS = 0X00) ......................................................................................... 212 5.2.2 THE TRANSMIT OVERHEAD DATA INPUT INTERFACE ...................................................................................... 212 FIGURE 63. SIMPLE ILLUSTRATION OF THE TRANSMIT OVERHEAD DATA INPUT INTERFACE BLOCK ......................................................... 212 TABLE 35: A LISTING OF THE OVERHEAD BITS WITHIN THE DS3 FRAME, AND THEIR POTENTIAL SOURCES, WITHIN THE XRT74L74 IC .... 213 TABLE 36: DESCRIPTION OF METHOD 1 TRANSMIT OVERHEAD INPUT INTERFACE SIGNALS ................................................................... 214 FIGURE 64. ILLUSTRATION OF THE TERMINAL EQUIPMENT BEING INTERFACED TO THE TRANSMIT OVERHEAD DATA INPUT INTERFACE (METHOD 1) ....................................................................................................................................................................................... 215 TABLE 37: THE RELATIONSHIP BETWEEN THE NUMBER OF RISING CLOCK EDGES IN TXOHCLK, (SINCE TXOHFRAME WAS LAST SAMPLED "HIGH") TO THE DS3 OVERHEAD BIT, THAT IS BEING PROCESSED ..................................................................................................... 216 FIGURE 65. ILLUSTRATION OF THE SIGNAL THAT MUST OCCUR BETWEEN THE TERMINAL EQUIPMENT AND THE XRT74L74, IN ORDER TO CONFIG- |
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