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XRT74L74IB Datasheet(PDF) 1 Page - Exar Corporation |
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XRT74L74IB Datasheet(HTML) 1 Page - Exar Corporation |
1 / 498 page Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com PRELIMINARY XRT74L74 4 CHANNEL, ATM UNI/PPP DS3/E3 FRAMING CONTROLLER OCTOBER 2003 REV. P1.1.1 GENERAL DESCRIPTION The XRT74L74 4 Channel, ATM UNI/PPP Physical Layer Processor with integrated DS3/E3 framing con- troller is designed to support ATM direct mapping and cell delineation as well as PPP mapping and Frame processing. For ATM UNI applications, this device provides the ATM Physical Layer (Physical Medium Dependent and Transmission Convergence sub-lay- ers) interface for the public and private networks at DS3/E3 rates. For Clear-Channel Framer applica- tions, this device supports the transmission and re- ception of “user data” via the DS3/E3 payload. The XRT74L74 DS3 ATM UNI/Clear-Channel Framer incorporates Receive, Transmit, Microprocessor Inter- face, Performance Monitor, Test and Diagnostic and Line Interface Unit Scan Drive functional sections. FEATURES • Compliant with 8/16 bit UTOPIA Level I and II and PPP Multi-PHY Interface Specifications and sup- ports UTOPIA Bus operating at 25, 33 or 50 MHz • Contains on-chip 16 cell FIFO (configurable in depths of 4, 8, 12 or 16 cells), in both the Transmit (TxFIFO) and Receive Directions (RxFIFO) • Contains on-chip 54 byte Transmit and Receive OAM Cell Buffer for transmission, reception and processing of OAM Cells • Supports ATM cell or PPP Packet Mapping • Supports M13 and C-Bit Parity Framing Formats • Supports DS3/E3 Clear-Channel Framing Applica- tions • Includes PRBS Generator and Receiver • Supports Line, Cell, and PLCP Loop-backs • Interfaces to 8 Bit wide Intel, Motorola, PowerPC, and Mips µPs • HDLC controller per channel for Tx and Rx • Low power 3.3V, 5V Input Tolerant, CMOS • Available in 388 pin PBGA Package APPLICATIONS • Digital Access and Cross Connect Systems • Digital, ATM, WAN and LAN Switches • Network Interface Service Units FIGURE 1. BLOCK DIAGRAM OF THE XRT74L74 ATM UNI/PPP DS3/E3 FRAMING CONTROLLER JTAG JTAG Microprocessor Interface (Programmable Registers and Interrupt Block) Microprocessor Interface (Programmable Registers and Interrupt Block) A[6:0] WR_RW RD_DS ALE_AS Reset D[7:0] µPClk RDY_DTCK CS INT Type Type_0 Type_1 Pblast PDBEN Transmitter_n Transmitter_n Receiver_n Receiver_n Performance Monitor Channel (n) Performance Monitor Channel (n) LAPD Transceiver Channel (n) LAPD Transceiver Channel (n) FEAC Processor Channel (n) FEAC Processor Channel (n) Note: Typical channel (n) shown, where; n = 0, 1, 2 or 3. Receive Cell Processor RxCellRxed_n RxGFCClk_n RxGFCMS_n RxGFC_n RxLCD_n Receive PLCP Processor/ Clear Channel Rx Serial Data Processor RxPOH_n RxPOHFrame_n RxPOHClk_n RxPFrame_n RxPLOF_n RxPOOF_n RxPRed_n HDLC CONTROLLER RXOHInd_n RxFrame_n RxClk_n RxOutClk_n RxNib_[3:0]_n RxSerData_n TDI TCK TMS TDO TRST ValidFCS_n RxIdle_n RxHDLCDat_[7:0]_n RxHDLCClk_n Rx Utopia/PPP Interface RxUClk RxUClkO RxUEn/RxPEnb RxUPrty RxUData[15:0]/RxPData[15:0] RxUSoC/RxPSOP RxUClav RxUAddr[4:0] RxTSX/RxPSOF RxPDVAL RxPERR RxPEOP RxMOD_n Line Interface Drive and Scan Tx Utopia/PPP Interface TxUClk TxUClkO TxUData[15:0]/TxPData[15:0] TxUPrty TxUSoC/TxPSOP TxUEn TxUClav TxUAddr[4:0] TxPEOP TxMod_n TxTSX/TxPOSF TxPERR HDLC CONTROLLER TXOHInd_n TxNibFrame_n Transmit Cell Processor TxGFCClk TxGFCMS_n TxGFC_n TxCellTxed_n TxNibClk_n TxFrameRef_n TxNib_[3:0]_n TxSerData_n TxHDLCClk_n TxHDLCDat_[7:0]_n SendFCS_n SendMSG_n Transmit PLCP Processor/ Clear Channel Tx Serial Data Processor TxStuffCtl_n 8KRef_n TxPOHClk_n TxPFrame_n TxPOH_n TxPOHFrame_n TxPOHIns_n EncoDis_n TxOH_n TxOHEnable_n Transmit DS3/E3 Framer TxPOS_n TxNEG_n TxFrame_n TxOHClk_n TxLineClk_n TxAISEn_n TxInClk_n TxOHIns_n TxOHFrame_n Receive DS3/E3 Framer RxLineClk_n RxNEG_n RxPOS_n RxSerClk_n RxOHEnable_n RxAIS_n RxOHClk_n RxOH_n RxLOS_n RxOOF_n EXTLOS_n RxOHFrame_n RxRed_n |
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