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XRT75L04DIV Datasheet(PDF) 7 Page - Exar Corporation |
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XRT75L04DIV Datasheet(HTML) 7 Page - Exar Corporation |
7 / 98 page áç áç áç áç XRT75L04D REV. 1.0.1 FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER 4 CHANNEL 1 ADDRESS LOCATION = 0X0E ................................................................. 83 CHANNEL 2 ADDRESS LOCATION = 0X16................................................................... 83 JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07 .................................................. 83 CHANNEL 1 ADDRESS LOCATION = 0X0F ..................................................... 83 CHANNEL 2 ADDRESS LOCATION = 0X17...................................................... 83 9.8.2 RECOMMENDATIONS ON PRE-PROCESSING THE GAPPED CLOCKS (FROM THE MAPPER/ASIC DEVICE) PRIOR TO ROUTING THIS DS3 CLOCK AND DATA-SIGNALS TO THE TRANSMIT INPUTS OF THE LIU ........................ 84 9.8.2.1 SOME NOTES PRIOR TO STARTING THIS DISCUSSION: ............................................................................ 84 JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07.................................................... 84 CHANNEL 1 ADDRESS LOCATION = 0X0F ............................................... 84 CHANNEL 2 ADDRESS LOCATION = 0X17................................................ 84 JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07.................................................... 84 CHANNEL 1 ADDRESS LOCATION = 0X0F .............................................. 84 CHANNEL 2 ADDRESS LOCATION = 0X17............................................... 84 9.8.2.2 OUR PRE-PROCESSING RECOMMENDATIONS ............................................................................................ 85 FIGURE 58. ILLUSTRATION OF MINOR PATTERN P1 ........................................................................................................................... 85 FIGURE 59. ILLUSTRATION OF MINOR PATTERN P2 ........................................................................................................................... 86 FIGURE 60. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE MAJOR PATTERN A ........................................................ 86 FIGURE 61. ILLUSTRATION OF MINOR PATTERN P3 ........................................................................................................................... 87 FIGURE 62. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE PATTERN B ..................................................................... 87 9.8.3 HOW DOES THE LIU PERMIT THE USER TO COMPLY WITH THE SONET APS RECOVERY TIME REQUIREMENTS OF 50MS (PER TELCORDIA GR-253-CORE)? ............................................................................................................ 88 FIGURE 63. ILLUSTRATION OF THE SUPER PATTERN WHICH IS OUTPUT VIA THE "OC-N TO DS3" MAPPER IC ..................................... 88 FIGURE 64. SIMPLE ILLUSTRATION OF THE LIU BEING USED IN A SONET DE-SYNCHRONIZER" APPLICATION........................................... 88 TABLE 24: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET ............................................................................... 89 JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07.................................................... 89 CHANNEL 1 ADDRESS LOCATION = 0X0F .............................................. 89 CHANNEL 2 ADDRESS LOCATION = 0X17............................................... 89 9.8.4 HOW SHOULD ONE CONFIGURE THE LIU, IF ONE NEEDS TO SUPPORT "DAISY-CHAIN" TESTING AT THE END CUSTOMER'S SITE?..................................................................................................................................................... 90 JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07.................................................... 90 CHANNEL 1 ADDRESS LOCATION = 0X0F ..................................................... 90 CHANNEL 2 ADDRESS LOCATION = 0X17...................................................... 90 APPENDIX B ................................................................................................................................. 91 TABLE 25: TRANSFORMER RECOMMENDATIONS......................................................................................................................... 91 TABLE 26: TRANSFORMER DETAILS....................................................................................................................................................... 91 ORDERING INFORMATION .................................................................................................................. 93 PACKAGE DIMENSIONS - 176 PIN PACKAGE ................................................................................................................. 93 REVISIONS .................................................................................................................................................................. 94 |
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