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XRT75L04DIV Datasheet(PDF) 8 Page - Exar Corporation |
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XRT75L04DIV Datasheet(HTML) 8 Page - Exar Corporation |
8 / 98 page XRT75L04D áç áç áç áç FOUR CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER REV. 1.0.1 4 PIN DESCRIPTIONS (BY FUNCTION) TRANSMIT INTERFACE PIN #SIGNAL NAME TYPE DESCRIPTION 52 49 169 172 TxON_0 TxON_1 TxON_2 TxON_3 I Transmitter ON Input - Channel 0: Transmitter ON Input - Channel 1: Transmitter ON Input - Channel 2: Transmitter ON Input - Channel 3: These pins are active only when the corresponding TxON bit is set. Table below shows the status of the transmitter based on theTxON bit and TxON pin settings. NOTES: 1. These pins will be active and can control the TTIP and TRING outputs only when the TxON_n bits in the channel register are set . 2. When Transmitters are turned off the TTIP and TRING outputs are Tri- stated. 3. These pins are internally pulled up. 46 34 175 11 TxCLK_0 TxCLK_1 TxCLK_2 TxCLK_3 I Transmit Clock Input for TPOS and TNEG - Channel 0: Transmit Clock Input for TPOS and TNEG - Channel 1: Transmit Clock Input for TPOS and TNEG - Channel 2: Transmit Clock Input for TPOS and TNEG - Channel 3: The frequency accuracy of this input clock must be of nominal bit rate ± 20 ppm. The duty cycle can be 30%-70%. By default, input data is sampled on the falling edge of TxCLK when input data is changing on the rising edge of TxCLK.. 44 32 1 13 TNEG_0 TNEG_1 TNEG_2 TNEG_3 I Transmit Negative Data Input - Channel 0: Transmit Negative Data Input - Channel 1: Transmit Negative Data Input - Channel 2: Transmit Negative Data Input - Channel 3: In Dual-rail mode, these pins are sampled on the falling or rising edge of TxCLK_n . NOTES: 1. These input pins are ignored and must be grounded if the Transmitter Section is configured to accept Single-Rail data from the Terminal Equipment. Bit 0 0 Transm itter Status OFF OFF Pin 0 1 1 1 OFF ON 0 1 Host/HW 1 1 1 1 x OFF 0 0 x ON 1 0 |
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