Electronic Components Datasheet Search |
|
XRT75L06D Datasheet(PDF) 7 Page - Exar Corporation |
|
XRT75L06D Datasheet(HTML) 7 Page - Exar Corporation |
7 / 103 page xr XRT75L06D REV. 1.0.4 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER IV CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06.................................................... 87 CHANNEL 1 ADDRESS LOCATION = 0X0E................................................. 87 CHANNEL 2 ADDRESS LOCATION = 0X16 .................................................. 87 JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07.................................. 87 CHANNEL 1 ADDRESS LOCATION = 0X0F..................................... 87 CHANNEL 2 ADDRESS LOCATION = 0X17 ..................................... 87 JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07................................... 88 CHANNEL 1 ADDRESS LOCATION = 0X0F............................... 88 CHANNEL 2 ADDRESS LOCATION = 0X17 ............................... 88 JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07................................... 88 CHANNEL 1 ADDRESS LOCATION = 0X0F.............................. 88 CHANNEL 2 ADDRESS LOCATION = 0X17 .............................. 88 7.8.2 RECOMMENDATIONS ON PRE-PROCESSING THE GAPPED CLOCKS (FROM THE MAPPER/ASIC DEVICE) PRIOR TO ROUTING THIS DS3 CLOCK AND DATA-SIGNALS TO THE TRANSMIT INPUTS OF THE LIU ........................ 88 FIGURE 66. ILLUSTRATION OF MINOR PATTERN P1 .................................................................................................................... 89 FIGURE 67. ILLUSTRATION OF MINOR PATTERN P2 .................................................................................................................... 90 FIGURE 68. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE MAJOR PATTERN A .................................................. 90 FIGURE 69. ILLUSTRATION OF MINOR PATTERN P3 .................................................................................................................... 91 FIGURE 70. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE PATTERN B............................................................... 91 FIGURE 71. ILLUSTRATION OF THE SUPER PATTERN WHICH IS OUTPUT VIA THE "OC-N TO DS3" MAPPER IC ............................... 92 FIGURE 72. SIMPLE ILLUSTRATION OF THE LIU BEING USED IN A SONET DE-SYNCHRONIZER" APPLICATION .................................... 92 7.8.3 HOW DOES THE LIU PERMIT THE USER TO COMPLY WITH THE SONET APS RECOVERY TIME REQUIREMENTS OF 50MS (PER TELCORDIA GR-253-CORE)? ............................................................................................................ 92 TABLE 21: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET ......................................................................... 93 JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07................................... 93 CHANNEL 1 ADDRESS LOCATION = 0X0F.............................. 93 CHANNEL 2 ADDRESS LOCATION = 0X17 .............................. 93 7.8.4 HOW SHOULD ONE CONFIGURE THE LIU, IF ONE NEEDS TO SUPPORT "DAISY-CHAIN" TESTING AT THE END CUSTOMER'S SITE?..................................................................................................................................................... 94 JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07................................... 94 CHANNEL 1 ADDRESS LOCATION = 0X0F..................................... 94 CHANNEL 2 ADDRESS LOCATION = 0X17 ..................................... 94 8.0 ELECTRICAL CHARACTERISTICS ..................................................................................................... 95 TABLE 22: ABSOLUTE MAXIMUM RATINGS ....................................................................................................................................... 95 TABLE 23: DC ELECTRICAL CHARACTERISTICS: ..............................................................................................................................95 APPENDIX A ................................................................................................................... 96 TABLE 24: TRANSFORMER RECOMMENDATIONS .................................................................................................................. 96 TABLE 25: TRANSFORMER DETAILS ................................................................................................................................................ 96 ORDERING INFORMATION ................................................................................................................. 98 PACKAGE DIMENSIONS - 23 X 23 MM 217 LEAD BGA PACKAGE .................................................................. 98 |
Similar Part No. - XRT75L06D |
|
Similar Description - XRT75L06D |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |