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XRT75L06IB Datasheet(PDF) 4 Page - Exar Corporation |
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XRT75L06IB Datasheet(HTML) 4 Page - Exar Corporation |
4 / 63 page XRT75L06 SIX CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH JITTER ATTENUATOR REV. 1.0.3 I TABLE OF CONTENTS GENERAL DESCRIPTION ................................................................................................. 1 APPLICATIONS .............................................................................................................................................. 1 Figure 1. Block Diagram of the XRT 75L06 ...................................................................................................... 1 ORDERING INFORMATION ................................................................................................................... 1 FEATURES .................................................................................................................................................... 2 TRANSMIT INTERFACE CHARACTERISTICS ...................................................................................................... 2 RECEIVE INTERFACE CHARACTERISTICS ........................................................................................................ 2 Figure 2. XRT75L06 in BGA package (Bottom View) ....................................................................................... 3 PIN DESCRIPTIONS (BY FUNCTION) .............................................................................. 4 TRANSMIT INTERFACE ................................................................................................................................... 4 RECEIVE INTERFACE ..................................................................................................................................... 6 CLOCK INTERFACE ........................................................................................................................................ 8 CONTROL AND ALARM INTERFACE ....................................................................................................... 9 ANALOG POWER AND GROUND ................................................................................................................... 12 DIGITAL POWER AND GROUND ..................................................................................................................... 14 1.0 clock Synthesizer ............................................................................................................................. 16 1.1 CLOCK DISTRIBUTION ....................................................................................................................................... 16 Figure 4. Clock Distribution Congifured in E3 Mode Without Using SFM ....................................................... 16 Figure 3. Simplified Block Diagram of the Input Clock Circuitry Driving the Microprocessor .......................... 16 2.0 The Receiver Section ....................................................................................................................... 17 Figure 5. Receive Path Block Diagram ........................................................................................................... 17 2.1 RECEIVE LINE INTERFACE ................................................................................................................................. 17 Figure 6. Receive Line InterfaceConnection ................................................................................................... 17 2.2 ADAPTIVE GAIN CONTROL (AGC) ..................................................................................................................... 18 2.3 RECEIVE EQUALIZER ........................................................................................................................................ 18 Figure 7. ACG/Equalizer Blcok Diagram ......................................................................................................... 18 2.3.1 Recommendations for Equalizer Settings ....................................................................................... 18 2.4 CLOCK AND DATA RECOVERY .......................................................................................................................... 18 2.4.1 Data/Clock Recovery Mode ............................................................................................................... 18 2.4.2 Training Mode ..................................................................................................................................... 18 2.5 LOS (LOSS OF SIGNAL) DETECTOR .................................................................................................................. 19 2.5.1 DS3/STS-1 LOS Condition ................................................................................................................. 19 2.5.2 Disabling ALOS/DLOS Detection ...................................................................................................... 19 TABLE 1: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF LOSTHR AND REQEN (DS3 AND STS-1 APPLICATIONS) ................................................................... 19 2.5.3 E3 LOS Condition: ............................................................................................................................. 20 Figure 8. Loss Of Signal Definition for E3 as per ITU-T G.775 ....................................................................... 20 Figure 9. Loss of Signal Definition for E3 as per ITU-T G.775. ....................................................................... 20 2.5.4 Interference Tolerance ....................................................................................................................... 21 Figure 10. Interference Margin Test Set up for DS3/STS-1 ............................................................................ 21 Figure 11. Interference Margin Test Set up for E3. ......................................................................................... 21 TABLE 2: INTERFERENCE MARGIN TEST RESULTS .............................................................................................. 22 2.5.5 Muting the Recovered Data with LOS condition: ............................................................................ 23 2.6 B3ZS/HDB3 DECODER .................................................................................................................................... 23 Figure 12. Receiver Data output and code violation timing ............................................................................ 23 3.0 The Transmitter Section .................................................................................................................. 24 Figure 13. Transmit Path Block Diagram ........................................................................................................ 24 3.1 TRANSMIT DIGITAL INPUT INTERFACE ................................................................................................................ 24 Figure 14. Typical interface between terminal equipment and the XRT75L06 (dual-rail data) ....................... 24 Figure 15. Transmitter Terminal Input Timing ................................................................................................. 25 Figure 16. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ......................................... 25 3.2 TRANSMIT CLOCK ............................................................................................................................................ 26 3.3 B3ZS/HDB3 ENCODER .................................................................................................................................... 26 |
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