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XRT75R12DIB Datasheet(PDF) 5 Page - Exar Corporation |
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XRT75R12DIB Datasheet(HTML) 5 Page - Exar Corporation |
5 / 131 page XRT75R12D TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER PRELIMINARY REV. P1.0.1 III TABLE 22: THE ABOVE IS: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR97 (ADDRESS LOCATION = 0X61) .................................. 63 TABLE 23: CHANNEL LEVEL INTERRUPT STATUS REGISTER - CR225 (ADDRESS LOCATION = 0XE1)....................................................... 63 TABLE 24: DEVICE/PART NUMBER REGISTER - CR110 (ADDRESS LOCATION = 0X6E) ........................................................................... 64 TABLE 25: CHIP REVISION NUMBER REGISTER - CR111 (ADDRESS LOCATION = 0X6F) ......................................................................... 64 THE PER-CHANNEL REGISTERS........................................................................................................................... 65 REGISTER DESCRIPTION - PER CHANNEL REGISTERS ....................................................................................66 TABLE 26: XRT75R12D REGISTER MAP SHOWING INTERRUPT ENABLE REGISTERS (IER_N) ............................................................... 66 TABLE 27: SOURCE LEVEL INTERRUPT ENABLE REGISTER - CHANNEL N ADDRESS LOCATION = 0XM1 .................................................... 66 TABLE 28: XRT75R12D REGISTER MAP SHOWING INTERRUPT STATUS REGISTERS (ISR_N) ............................................................... 68 TABLE 29: SOURCE LEVEL INTERRUPT STATUS REGISTER - CHANNEL N ADDRESS LOCATION = 0XM2 .................................................... 68 TABLE 30: XRT75R12D REGISTER MAP SHOWING ALARM STATUS REGISTERS (AS_N)........................................................................ 70 TABLE 31: ALARM STATUS REGISTER - CHANNEL N ADDRESS LOCATION = 0XM3................................................................................... 70 TABLE 32: XRT75R12D REGISTER MAP SHOWING TRANSMIT CONTROL REGISTERS (TC_N) ................................................................ 74 TABLE 33: TRANSMIT CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM4 ........................................................................... 74 TABLE 34: XRT75R12D REGISTER MAP SHOWING RECEIVE CONTROL REGISTERS (RC_N).................................................................. 76 TABLE 35: RECEIVE CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM5 ............................................................................. 76 TABLE 36: XRT75R12D REGISTER MAP SHOWING CHANNEL CONTROL REGISTERS (CC_N)................................................................. 77 TABLE 37: CHANNEL CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM6 ............................................................................ 77 TABLE 38: XRT75R12D REGISTER MAP SHOWING JITTER ATTENUATOR CONTROL REGISTERS (JA_N)................................................. 80 TABLE 39: JITTER ATTENUATOR CONTROL REGISTER - CHANNEL N ADDRESS LOCATION = 0XM7 ........................................................... 80 TABLE 40: XRT75R12D REGISTER MAP SHOWING ERROR COUNTER MSBYTE REGISTERS (EM_N) ..................................................... 81 TABLE 41: ERROR COUNTER MSBYTE REGISTER - CHANNEL N ADDRESS LOCATION = 0XMA................................................................. 81 TABLE 42: XRT75R12D REGISTER MAP SHOWING ERROR COUNTER LSBYTE REGISTERS (EL_N) ....................................................... 82 TABLE 43: ERROR COUNTER LSBYTE REGISTER - CHANNEL N ADDRESS LOCATION = 0XMB.................................................................. 82 TABLE 44: XRT75R12D REGISTER MAP SHOWING ERROR COUNTER HOLDING REGISTERS (EH_N) ..................................................... 82 TABLE 45: ERROR COUNTER HOLDING REGISTER - CHANNEL N ADDRESS LOCATION = 0XMC ................................................................ 83 8.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU ............................................................... 85 8.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS ........................... 85 FIGURE 37. A SIMPLE ILLUSTRATION OF A DS3 SIGNAL BEING MAPPED INTO AND TRANSPORTED OVER THE SONET NETWORK ............... 86 8.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................. 87 8.2.1 HOW DS3 DATA IS MAPPED INTO SONET ............................................................................................................. 87 FIGURE 38. A SIMPLE ILLUSTRATION OF THE SONET STS-1 FRAME ..................................................................................................... 88 FIGURE 39. A SIMPLE ILLUSTRATION OF THE STS-1 FRAME STRUCTURE WITH THE TOH AND THE ENVELOPE CAPACITY BYTES DESIGNATED 89 FIGURE 40. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME................................................................................................. 90 FIGURE 41. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME................................................................................................. 91 FIGURE 42. ILLUSTRATION OF THE BYTE STRUCTURE OF THE STS-1 SPE ............................................................................................. 92 FIGURE 43. AN ILLUSTRATION OF TELCORDIA GR-253-CORE’S RECOMMENDATION ON HOW MAP DS3 DATA INTO AN STS-1 SPE ......... 93 FIGURE 44. A SIMPLIFIED "BIT-ORIENTED" VERSION OF TELCORDIA GR-253-CORE’S RECOMMENDATION ON HOW TO MAP DS3 DATA INTO AN STS-1 SPE.......................................................................................................................................................................... 93 8.2.2 DS3 FREQUENCY OFFSETS AND THE USE OF THE "STUFF OPPORTUNITY" BITS ......................................... 94 FIGURE 45. A SIMPLE ILLUSTRATION OF A DS3 DATA-STREAM BEING MAPPED INTO AN STS-1 SPE, VIA A PTE .................................... 95 FIGURE 46. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE "SOURCE" PTE, WHEN MAPPING IN A DS3 SIGNAL THAT HAS A BIT RATE OF 44.736MBPS + 1PPM, INTO AN STS-1 SIGNAL .................................................................................. 96 8.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS .............................................................................. 98 8.3.1 THE CONCEPT OF AN STS-1 SPE POINTER........................................................................................................... 98 FIGURE 47. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE SOURCE PTE, WHEN MAPPING A DS3 SIGNAL THAT HAS A BIT RATE OF 44.736MBPS - 1PPM, INTO AN STS-1 SIGNAL................................................................................... 98 FIGURE 48. AN ILLUSTRATION OF AN STS-1 SPE STRADDLING ACROSS TWO CONSECUTIVE STS-1 FRAMES ........................................... 99 8.3.2 POINTER ADJUSTMENTS WITHIN THE SONET NETWORK ................................................................................ 100 FIGURE 49. THE BIT-FORMAT OF THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE 10 BITS, REFLECTING THE LOCATION OF THE J1 BYTE, DESIGNATED .................................................................................................................................................. 100 FIGURE 50. THE RELATIONSHIP BETWEEN THE CONTENTS OF THE "POINTER BITS" (E.G., THE 10-BIT EXPRESSION WITHIN THE H1 AND H2 BYTES) AND THE LOCATION OF THE J1 BYTE WITHIN THE ENVELOPE CAPACITY OF AN STS-1 FRAME ................................................ 100 8.3.3 CAUSES OF POINTER ADJUSTMENTS ................................................................................................................. 101 FIGURE 51. AN ILLUSTRATION OF AN STS-1 SIGNAL BEING PROCESSED VIA A SLIP BUFFER.................................................................. 102 FIGURE 52. AN ILLUSTRATION OF THE BIT FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "I" BITS DES- IGNATED ............................................................................................................................................................................. 103 FIGURE 53. AN ILLUSTRATION OF THE BIT-FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE "D" BITS DES- IGNATED ............................................................................................................................................................................. 104 8.3.4 WHY ARE WE TALKING ABOUT POINTER ADJUSTMENTS? ............................................................................. 105 8.4 CLOCK GAPPING JITTER ........................................................................................................................... 105 FIGURE 54. ILLUSTRATION OF THE TYPICAL APPLICATIONS FOR THE LIU IN A SONET DE-SYNC APPLICATION ...................................... 105 8.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE) |
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