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XRT84L38 Datasheet(PDF) 5 Page - Exar Corporation |
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XRT84L38 Datasheet(HTML) 5 Page - Exar Corporation |
5 / 451 page áç áç áç áç XRT84L38 OCTAL T1/E1/J1 FRAMER REV. 1.0.0 II Figure 15. Motorola µP Interface Signals during subsequent Write Operations of a Burst I/O Cy- cle ......................................................................................................................................... 68 DMA-0 Write DMA Interface ............................................................................................................................. 69 1.5 MEMORY AND REGISTER MAP .............................................................................................................. 69 1.5.1 Memory Mapped I/O Indirect Addressing ................................................................................. 69 Figure 16. DMA Mode for the XRT84L38 and a Microprocessor ................................................. 69 TABLE 8: ADDRESS MAP ..................................................................................................................... 70 1.6 DESCRIPTION OF THE CONTROL REGISTERS ......................................................................................... 71 RECEIVE SUBSTITUTION SIGNALING REGISTER (RSSR) (INDIRECT ADDRESS = 0XN02H, 0XC0H - 0XD7H) 150 TABLE 9: PMON T1/E1 RECEIVE LINE CODE (BIPOLAR) VIOLATION COUNTER ................................... 175 TABLE 10: PMON T1/E1 RECEIVE LINE CODE (BIPOLAR) VIOLATION COUNTER ................................. 175 TABLE 11: PMON T1/E1 RECEIVE FRAMING ALIGNMENT BIT ERROR COUNTER ................................. 175 TABLE 12: PMON T1/E1 RECEIVE FRAMING ALIGNMENT BIT ERROR COUNTER ................................. 175 TABLE 13: PMON T1/E1 RECEIVE SEVERELY ERRORED FRAME COUNTER ........................................ 176 TABLE 14: PMON T1/E1 RECEIVE CRC-4 BLOCK ERROR COUNTER - MSB ..................................... 176 TABLE 15: PMON T1/E1 RECEIVE CRC-4 BLOCK ERROR COUNTER - LSB ...................................... 176 TABLE 16: PMON T1/E1 RECEIVE FAR-END BLOCK ERROR COUNTER - MSB .................................. 176 TABLE 17: PMON T1/E1 RECEIVE FAR END BLOCK ERROR COUNTER .............................................. 177 TABLE 18: PMON T1/E1 RECEIVE SLIP COUNTER ............................................................................ 177 TABLE 19: PMON T1/E1 RECEIVE LOSS OF FRAME COUNTER .......................................................... 177 TABLE 20: PMON T1/E1 RECEIVE CHANGE OF FRAME ALIGNMENT COUNTER ................................... 178 TABLE 21: PMON LAPD T1/E1 FRAME CHECK SEQUENCE ERROR COUNTER ................................... 178 TABLE 22: T1/E1 PRBS BIT ERROR COUNTER MSB ........................................................................ 178 TABLE 23: T1/E1 PRBS BIT ERROR COUNTER LSB ......................................................................... 179 TABLE 24: T1/E1 TRANSMIT SLIP COUNTER ...................................................................................... 179 1.7 THE INTERRUPT STRUCTURE WITHIN THE FRAMER .............................................................................. 180 TABLE 25: LIST OF THE POSSIBLE CONDITIONS THAT CAN GENERATE INTERRUPTS, IN EACH FRAMER . 180 TABLE 26: ADDRESS OF THE BLOCK INTERRUPT STATUS REGISTERS ................................................. 181 TABLE 27: BLOCK INTERRUPT STATUS REGISTER .............................................................................. 182 TABLE 28: BLOCK INTERRUPT ENABLE REGISTER ............................................................................. 183 1.7.1 Configuring the Interrupt System, at the Framer Level ........................................................... 184 TABLE 29: INTERRUPT CONTROL REGISTER ....................................................................................... 184 2.0 The E1 Framing Structure .................................................................................................................... 186 2.1 THE SINGLE E1 FRAME ...................................................................................................................... 186 Timeslot 0 ....................................................................................................................................................... 186 Timeslot 0 octets within FAS frames .............................................................................................................. 186 Figure 17. Single E1 Frame Diagram ........................................................................................... 186 TABLE 30: BIT FORMAT OF TIMESLOT 0 OCTET WITHIN A FAS E1 FRAME .......................................... 186 Bit 0—Si (International Bit) ............................................................................................................................. 187 Bit 0—Si (International Bit) ............................................................................................................................. 187 Bit 1—Fixed at “1” .......................................................................................................................................... 187 Bit 2—A (FAS Frame Yellow Alarm Bit) ......................................................................................................... 187 Bit 3 through 7—Sa4–Sa8 (National Bits) ...................................................................................................... 187 2.2 THE E1 MULTI-FRAME STRUCTURES ................................................................................................... 187 2.2.1 The CRC Multi-frame Structure .............................................................................................. 187 TABLE 31: BIT FORMAT OF TIMESLOT 0 OCTET WITHIN A NON-FAS E1 FRAME .................................. 187 2.2.2 CAS Multi-Frames and Channel Associated Signaling .......................................................... 188 TABLE 32: BIT FORMAT OF ALL TIMESLOT 0 OCTETS WITHIN A CRC MULTI-FRAME ............................ 188 Figure 18. Frame/Byte Format of the CAS Multi-Frame Structure ............................................ 189 Figure 19. E1 Frame Format ......................................................................................................... 190 3.0 The DS1 Framing Structure ................................................................................................................. 191 3.1 T1 SUPER FRAME FORMAT (SF) ........................................................................................................ 191 Figure 20. T1 Frame Format ......................................................................................................... 191 Figure 21. T1 Superframe PCM Format ....................................................................................... 192 TABLE 33: SUPERFRAME FORMAT ..................................................................................................... 192 |
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