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XRT86SH328IB Datasheet(PDF) 10 Page - Exar Corporation

Part # XRT86SH328IB
Description  INTEGRATED 28-CHANNEL T1/E1 LIU/FRAMER, VT/TU MAPPER AND M13 MULTIPLEXER
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Manufacturer  EXAR [Exar Corporation]
Direct Link  http://www.exar.com
Logo EXAR - Exar Corporation

XRT86SH328IB Datasheet(HTML) 10 Page - Exar Corporation

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XRT86SH328
Datasheet
XRT86SH328 PIN DESCRIPTIONS
Datasheet
7
P1.0.1, September 1, 2005
R26
RDY/
DTACK/
RDY
O
READY or DTACK Output:
The function of this input pin depends upon which mode the Microprocessor Interface
has been configured to operate in.
Intel-Asynchronous Mode - RDY* - Ready Output:
If the Microprocessor Interface has been configured to operate in the Intel-
Asynchronous Mode, then this output pin will function as the active-low READY
output.During a READ or WRITE cycle, the Microprocessor Interface block will toggle
this output pin to the logic low level, ONLY when it (the Microprocessor Interface) is
ready to complete or terminate the current READ or WRITE cycle. Once the
Microprocessor has determined that this input pin has toggled to the logic "Low" level,
then it is now safe for it to move on and execute the next READ or WRITE cycle. If
(during a READ or WRITE cycle) the Microprocessor Interface block is holding this
output pin at a logic "High" level, then the Microprocessor is expected to extend this
READ or WRITE cycle, until it detects this output pin being toggled to the logic low
level.
Motorola-Asynchronous Mode - DTACK* - Data Transfer Acknowledge Output
If the Microprocessor Interface has been configured to operate in the Motorola-
Asynchronous Mode, then this output pin will function as the active-low DTACK
output.During a READ or WRITE cycle, the Microprocessor Interface block will toggle
this output pin to the logic low level, ONLY when it (the Microprocessor Interface) is
ready to complete or terminate the current READ or WRITE cycle. Once the
Microprocessor has determined that this input pin has toggled to the logic "Low" level,
then it is now safe for it to move on and execute the next READ or WRITE cycle. If
(during a READ or WRITE cycle) the Microprocessor Interface block is holding this
output pin at a logic "High" level, then the Microprocessor is expected to extend this
READ or WRITE cycle, until it detects this output pin being toggled to the logic low
level.
Power PC 403 Mode - RDY - Ready Output:
If the Microprocessor Interface has been configured to operate in the Power PC 403
Mode, then this output pin will function as the active-high READY output.During a
READ or WRITE cycle, the Microprocessor Interface block will toggle this output pin to
the logic high level, ONLY when it (the Microprocessor Interface) is ready to complete
or terminate the current READ or WRITE cycle. Once the Microprocessor has
sampled this signal being at the logic "High" level (upon the rising edge of PCLK), then
it is now safe for it to move on and execute the next READ or WRITE cycle. If (during
a READ or WRITE cycle) the Microprocessor Interface block is holding this output pin
at a logic "Low" level, then the Microprocessor is expected to extend this READ or
WRITE cycle, until it samples this output pin being at the logic low level.
Note: The Microprocessor Interface will update the state of this output pin upon the
rising edge of µPCLK.
P1
RESET
I
Hardware Reset Input:
When this active-low signal is asserted, the XRT79L71 device will be asynchronously
reset. When this occurs, all outputs will be tri-stated and all on-chip registers will be
reset to their default values.
Table 2
Microprocessor Interface - Pin Descriptions
Pin/Ball
Number
Pin Name
Type
Description


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