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XRT86VL32 Datasheet(PDF) 9 Page - Exar Corporation |
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XRT86VL32 Datasheet(HTML) 9 Page - Exar Corporation |
9 / 173 page xr PRELIMINARY XRT86VL32 REV. P1.0.5 DUAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION 4 DESCRIPTION OF THE CONTROL REGISTERS - E1 MODE All address on this register description is shown in HEX format, where n indicates channels 0 and 2 in the 2- channel device. TABLE 1: REGISTER SUMMARY FUNCTION SYMBOL HEX Control Registers (0xn100 - 0xn1FF) Clock and Select Register CSR 0xn100 Line Interface Control Register LICR 0xn101 Reserved - 0xn102 - 0xn106 Framing Select Register FSR 0xn107 Alarm Generation Register AGR 0xn108 Synchronization MUX Register SMR 0xn109 Transmit Signaling and Data Link Select Register TSDLSR 0xn10A Framing Control Register FCR 0xn10B Receive Signaling & Data Link Select Register RSDLSR 0xn10C Receive Signaling Change Register 0 RSCR0 0xn10D Receive Signaling Change Register 1 RSCR1 0xn10E Receive Signaling Change Register 2 RSCR2 0xn10F Receive Signaling Change Register 3 RSCR3 0xn110 Receive National Bits Register RNBR 0xn111 Receive Extra Bits Register REBR 0xn112 Data Link Control Register 1 DLCR1 0xn113 Transmit Data Link Byte Count Register 1 TDLBCR1 0xn114 Receive Data Link Byte Count Register 1 RDLBCR1 0xn115 Slip Buffer Control Register SBCR 0xn116 FIFO Latency Register FIFOLR 0xn117 DMA 0 (Write) Configuration Register D0WCR 0xn118 DMA 1 (Read) Configuration Register D1RCR 0xn119 Interrupt Control Register ICR 0xn11A LAPD Select Register LAPDSR 0xn11B Reserved - T1 mode only - 0xn11C Performance Report Control Register PRCR 0xn11D Gapped Clock Control Register GCCR 0xn11E Transmit Interface Control Register TICR 0xn120 PRBS Control & Status Register 0 PRBSCSR0 0xn121 |
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