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XRT86VL38IB484 Datasheet(PDF) 11 Page - Exar Corporation |
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XRT86VL38IB484 Datasheet(HTML) 11 Page - Exar Corporation |
11 / 149 page XRT86VL3X 4 REV. 1.2.0 T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION 1.0 GENERAL DESCRIPTION AND INTERFACE The XRT86VL3x supports multiple interfaces for various modes of operation. The purpose of this section is to present a general overview of the common interfaces and their connection diagrams. Each mode will be described in full detail in later sections of the datasheet. NOTE: For a brief tutorial on Framing Formats, see Appendix A in the back of this document. 1.1 Physical Interface The Line Interface Unit generates/receives standard return-to-zero (RZ) signals to the line interface for T1/E1/ J1 twisted pair or E1 coaxial cable. The physical interface is optimized by placing the terminating impedance inside the LIU. This allows one bill of materials for all modes of operation reducing the number of external components necessary in system design. The transmitter outputs only require one DC blocking capacitor of 0.68µF and a 1:2 step-up transformer. The receive path inputs only require one bypass capacitor of 0.1 µF connected to the center tap (CT) of the transformer and a 1:1 transformer. The receive CT bypass capacitor is required for Long Haul Applications, and recommended for Short Haul Applications. Figure 2 shows the typical connection diagram for the LIU transmitters. Figure 3 shows a typical connection diagram for the LIU receivers. FIGURE 2. LIU TRANSMIT CONNECTION DIAGRAM USING INTERNAL TERMINATION FIGURE 3. LIU RECEIVE CONNECTION DIAGRAM USING INTERNAL TERMINATION T TIP T RING XRT86VL3x LIU 1:2 Internal Impedance Line Interface T1/E1/J1 C=0.68uF One Bill of Materials Transmitter Output R TIP R RING XRT86VL3x LIU 1:1 Internal Impedance Line Interface T1/E1/J1 One Bill of Materials Receiver Input 0.1 µF |
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