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XRT91L80 Datasheet(PDF) 8 Page - Exar Corporation |
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XRT91L80 Datasheet(HTML) 8 Page - Exar Corporation |
8 / 41 page XRT91L80 PRELIMINARY xr xr xr xr 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER REV. P1.0.4 6 TRANSMITTER SECTION NAME LEVEL TYPE PIN DESCRIPTION TXDI0P TXDI0N TXDI1P TXDI1N TXDI2P TXDI2N TXDI3P TXDI3N LVDS I H13 J13 K14 L14 K13 L13 M14 N14 Transmit Parallel Data Input The 622Mbps 4-bit parallel transmit input data should be applied to the transmitters simultaneously referenced to the ris- ing edge of the TXCLKI input. The 4-bit parallel interface is multiplexed into the transmit serial output interface MSB first (TXDI3P/N). NOTE: The XRT91L80 can accept 666Mbps 4-bit parallel transmit input data for Forward Error Correction (FEC) Applications. TXCLKIP TXCLKIN LVDS I H14 J14 Transmit Input Clock 622MHz input clock reference for the 4-bit parallel transmit input data TXDIP/N[3:0]. NOTE: The XRT91L80 can accept a 666MHz transmit input clock for Forward Error Correction (FEC) Applications. TXOP TXON CMLDIFF O K1 L1 Transmit Serial Data Output The transmit serial data stream is generated by multiplexing the 4-bit parallel transmit input data into a 2.488Gbps serial data stream. In Forward Error Correction, the transmit serial data stream is 2.666Gbps. REFCLKP REFCLKN LVPECL I P6 N6 Reference Clock Input This differential input clock reference is used for the transmit clock multiplier unit (CMU) to provide the necessary high speed clock reference for this device. Pin REFFREQSEL determines the value used as the reference. See Pin REFFREQSEL for more details. VCXO_INP VCXO_INN LVPECL I P4 N4 Voltage Controled Oscillator Input This differential input clock is used for the transmit PLL jitter attenuation. Pin REFFREQSEL determines the value used as the reference. See Pin REFFREQSEL for more details. REFFREQSEL LVTTL I P1 Reference Clock Frequency Select Hardware Mode This pin is used to select the frequency of the REFCLK input to the CMU. "Low" = 77.76MHz (83.5MHz for FEC) "High" = 155.52MHz (167MHz for FEC) This pin is provided with an internal active pull-down. VCXO_SEL LVTTL I M6 Selects De-Jitter VCXO Option Hardware Mode This pin selects either the normal REFCLK or the de-jitter VCXO as a reference clock. "Low" = Normal REFCLK Mode "High" = De-Jitter VCXO Mode This pin is provided with an internal active pull-down. VCXO_LOCK LVTTL O N8 De-Jitter PLL Lock Detect If the de-jitter PLL lock detect is enabled with Pin P3 and the de-jitter VCXO mode is selected by Pin M6, this pin will pull "High" when the PLL is locked. "Low" = VCXO out of Lock "High" = VCXO Locked |
Similar Part No. - XRT91L80 |
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Similar Description - XRT91L80 |
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