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XRT91L82 Datasheet(PDF) 10 Page - Exar Corporation |
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XRT91L82 Datasheet(HTML) 10 Page - Exar Corporation |
10 / 59 page XRT91L82 PRELIMINARY xr xr xr xr 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER REV. P1.0.5 7 DLOOP LVTTL, LVCMOS I E11 Digital Local Loopback The digital local loopback mode interconnects the 16-bit parallel transmit data and parallel transmit clock input to the 16-bit par- allel receive data and parallel receive clock output respectively while maintaining the transmit serial data output. If digital local loopback is enabled, the receive serial data input is ignored. "Low" = Digital Local Loopback Mode Enabled "High" = Disabled This pin is provided with an internal pull-up. LOOPTM_NOJA / SDI LVTTL, LVCMOS I C10 Loop Timing Mode With No Jitter Attenuation Hardware Mode When the loop timing mode is activated, the external local reference clock input to the CMU is replaced with the 1/16th of the high-speed recovered receive clock coming from the CDR. "Low" = Disabled "High" = Loop timing Activated This pin is provided with an internal pull-down. Host Mode This pin is functions as the microprocessor Serial Data Input. COMMON CONTROL NAME LEVEL TYPE PIN DESCRIPTION |
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