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XRT95L53 Datasheet(PDF) 2 Page - Exar Corporation |
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XRT95L53 Datasheet(HTML) 2 Page - Exar Corporation |
2 / 4 page XRT95L53 EX tendAR-48M xr OC-48 ETHERNET/SONET MULTI-SERVICE FRAMER PROCESSOR REV. P1.0.0 2 • Supports mapping of data using POS/HDLC framing into SONET/SDH in accordance with RFC2615 & IETF 1662 ■ Optionally supports PPP/BCP (Bridging Control Protocol) encapsulation ■ Performs ATM cell de-lineation and maps ATM packets into SONET/SDH using POS/HDLC • Support for 48 DS3 and sub-rate DS3 framers on-chip ■ Maps/De-maps DS3 signals into SONET/SDH payloads ■ Supports extensive performance monitoring on DS3 data ■ Integrated fractional DS3/T3 and scrambling functions • Supports mapping of Ethernet data over SDH using LAPS framing according to ITU-T X.86 • Supports a 32 bit micro-processor interface for management, configuration, gathering extended statistics and providing interrupts for alarm processing • Supports performance monitoring and alarms as required by GR.253, G.707 and ANSI T1.105 FIGURE 1. XRT95L53 EX tendAR-48M BLOCK DIAGRAM ORDERING INFORMATION PART NUMBER PACKAGE TYPE OPERATING TEMPERATURE RANGE XRT95L53 PBGA 780 -40°C to 85°C STS-48 4-bit @622Mhz 4xSTS-12/STS-3 OC-48 Serdes 4x OC-12 Serdes Section/Line/ TOH Processor Section/Line/ TOH Processor Pointer Proc. STS-1 Path Overhead Processor and Cross Connect GFP LAPS PPP ATM GFP LAPS PPP ATM VC LCAS VC LCAS JTAG Interface Overhead Add/Drop Bus 32 bit uProcessor Interface SDRAM Interface DS3/ Sub-rate DS3 Framers DS3/ Sub-rate DS3 Framers STS-12 (Add/drop port) 4x1-bit@622Mhz SPI-3 Interface POS-PHY 3 G-Header Interface PRELIMINARY |
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