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UT7C139C45GCC Datasheet(PDF) 4 Page - Aeroflex Circuit Technology |
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UT7C139C45GCC Datasheet(HTML) 4 Page - Aeroflex Circuit Technology |
4 / 21 page 4 The UT7C138/139 consists of an array of 4K words of 8 or 9 bits of dual-port SRAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. With the M/S pin, the UT7C138/139 can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). Each port is provided with its own output enable control (OE), which allows data to be read from the device. WRITE CYCLE A combination of R/W less than VIL (max), and CE less than VIL (max), defines a write cycle. The state of OE is a “don’t care” for a write cycle. The outputs are placed in the high- impedance state when either OE is greater than VIH (min), or when R/W is less than VIL (max). WRITE OPERATION Write Cycle 1, the Write Enable-controlled Access shown in figure 4a, is defined by a write terminated by R/W going high with CE active. The write pulse width is defined by tPWE when the write is initiated by R/W, and by tSCE when the write is initiated by CE going active. Unless the outputs have been previously placed in the high-impedance state by OE, the user must wait t HZOE before applying data to the eight/nine bidirectional pins I/O(0:7/0:8) to avoid bus contention. Write Cycle 2, the Chip Enable-controlled Access shown in figure 4b, is defined by a write terminated byCE going inactive. The write pulse width is defined by tPWE when the write is initiated by R/W, and by tSCE when the write is initiated by CE going active. For the R/W initiated write, unless the outputs have been previously placed in the high-impedance state by OE, the user must wait t HZWE before applying data to the eight/nine bidirectional pins I/O(0:7/0:8) to avoid bus contention. If a location is being written by one port and the opposite port attempts to read that location, a port-to-port flow through delay must be met before the data is read on the output. Data will be valid on the port wishing to read the location (t BZA + t BDD) after the data is written on the other port (see figure 5a). READ OPERATION When reading the device, the user must assert both the OE and CE pins. Data will be available t ACE after CE or tDOE after OE is asserted (see figures 3a and 3b). MASTER/SLAVE A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. Writing of slave devices must be delayed until after the BUSY input has settled. Otherwise, the slave chip may begin a write cycle during a contention situation. When presented as a HIGH input, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. When presented as a LOW input, the M/S pin allows the device to be used as a slave, and, therefore, the BUSY pin is an input. Table 1. Non-Contending Read/Write RADIATION HARDNESS The UT7C138/139 incorporates special design and layout features which allow operation in high-level radiation environments. UTMC has developed special low-temperature processing techniques designed to enhance the total-dose radiation hardness of both the gate oxide and the field oxide while maintaining the circuit density and reliability. For transient radiation hardness and latchup immunity, UTMC builds all radiation-hardened products on epitaxial wafers using an advanced twin-tub CMOS process. In addition, UTMC pays special attention to power and ground distribution during the design phase, minimizing dose-rate upset caused by rail collapse. Table 2. Radiation Hardness Design Specifications1 Notes: 1. The DPRAM will not latchup during radiation exposure under recommended operating conditions. 2. Not tested for CMOS technology. INPUTS OUTPUTS CE R/W OE I/O0-7 OPERATION H X X High Z Power Down X X H High Z I/O Lines Disabled L H L Data Out Read L L X Data In Write L X X --- Illegal Condition Total Dose 1.0E6 rads(Si) LET Threshold 85 MeV-cm2/mg Neutron Fluence2 3.0E14 n/cm2 Memory Device Cross Section @ LET = 120MeV-cm 2/mg < 1.376E -2 (4Kx8) < 1.548E -2 (4Kx9) cm2 |
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