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K6R4016V1C-C12 Datasheet(PDF) 5 Page - Samsung semiconductor |
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K6R4016V1C-C12 Datasheet(HTML) 5 Page - Samsung semiconductor |
5 / 11 page K6R4016V1C-C/C-L, K6R4016V1C-I/C-P CMOS SRAM PRELIMPreliminaryPPPPPPPPPINARY Rev 5.0 - 5 - September 2001 TEST CONDITIONS* * The above test conditions are also applied at industrial temperature range. Parameter Value Input Pulse Levels 0V to 3V Input Rise and Fall Times 3ns Input and Output timing Reference Levels 1.5V Output Loads See below AC CHARACTERISTICS(TA=0 to 70 °C, VCC=3.3±0.3V, unless otherwise noted.) Output Loads(B) DOUT 5pF* 319 Ω 353 Ω for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +3.3V * Including Scope and Jig Capacitance Output Loads(A) DOUT RL = 50 Ω ZO = 50 Ω VL = 1.5V 30pF* * Capacitive Load consists of all components of the test environment. READ CYCLE* * The above parameters are also guaranteed at industrial temperature range. Parameter Symbol K6R4016V1C-10 K6R4016V1C-12 K6R4016V1C-15 Unit Min Max Min Max Min Max Read Cycle Time tRC 10 - 12 - 15 - ns Address Access Time tAA - 10 - 12 - 15 ns Chip Select to Output tCO - 10 - 12 - 15 ns Output Enable to Valid Output tOE - 5 - 6 - 7 ns UB, LB Access Time tBA - 5 - 6 - 7 ns Chip Enable to Low-Z Output tLZ 3 - 3 - 3 - ns Output Enable to Low-Z Output tOLZ 0 - 0 - 0 - ns UB, LB Enable to Low-Z Output tBLZ 0 - 0 - 0 - ns Chip Disable to High-Z Output tHZ 0 5 0 6 0 7 ns Output Disable to High-Z Output tOHZ 0 5 0 6 0 7 ns UB, LB Disable to High-Z Output tBHZ 0 5 0 6 0 7 ns Output Hold from Address Change tOH 3 - 3 - 3 - ns |
Similar Part No. - K6R4016V1C-C12 |
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