HANBit

HSD16M64F8V/VA

HANBit Electronics Co.,Ltd.

REV.1.0 (August.2002)

7

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and

then rounding off to the next higher integer.

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. For -8/H/L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .

(Recommand : tRDL=2CLK and tDAL=2CLK & 20ns.)

AC CHARACTERISTICS

(AC operating conditions unless otherwise noted)

-13

-12

-10

-10L

PARAMETER

SYMBOL

MIN

MAX

MIN

MAX

MIN

MAX

MIN

MAX

UNIT

NOTE

CAS

latency=3

7.5

8

10

10

CLK cycle time

CAS

latency=2

-

1000

-

1000

10

1000

12

1000

ns

1

CAS

latency=3

5.4

6

6

6

CLK to valid

output delay

CAS

latency=2

-

-

6

7

ns

1,2

CAS

latency=3

2.7

3

3

3

Output data

hold time

CAS

latency=2

-

-

3

3

ns

2

CLK high pulse width

2.5

3

3

3

ns

3

CLK low pulse width

2.5

3

3

3

ns

3

Input setup time

1.5

2

2

2

ns

3

Input hold time

0.8

1

1

1

ns

3

CLK to output in Low-Z

1

1

1

1

ns

3

CAS

latency=3

5.4

6

6

6

ns

2

CLK to output

in Hi-Z

CAS

latency=2

-

-

6

7

ns

Notes :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.

If tr & tf is longer than 1ns, transient time compensation should be considered, ie., [(tr + tf)/2-1]ns should be added to

the parameter.