Rev. 9/09/97

4/15

64K x 32 Burst

GS820V32Q/T

4/5/6, 2.5V I/O, 2.0mA

80-133MHz (P/L)

66MHz Flow-Thru

G S I T E C H N O L O G Y

GS820V32Q/T

Synchronous truth table

Note:

1. X=don’t care, H=logic high, L=logic low

2. BWx is the logic function of GW, BWE, BW1, BW2, BW3, BW4. See Byte Write Function table for detail.

3. All inputs in the table must meet setup and hold on rising edge of CLK.

DQ Bus Control and Asynchronous OE

Note: On the write cycle that follows read cycle, OE need to be held high prior to the start of write cycle to tri-state DQ buss and allow data

input to SRAM.

Cycle

Address used

CE1

CE2

CE3 ADSP ADSC ADV BWx

Deselect

none

H

X

X

X

L

X

X

Deselect

none

L

L

X

X

L

X

X

Deselect

none

L

X

H

X

L

X

X

Deselect

none

L

L

X

L

X

X

X

Deselect

none

L

X

H

L

X

X

X

Read, begin burst

external

L

H

L

L

X

X

X

Read, begin burst

external

L

H

L

H

L

X

H

Read, continue burst

next

X

X

X

H

H

L

H

Read, continue burst

next

H

X

X

X

H

L

H

Read, suspend burst

current

X

X

X

H

H

H

H

Read, suspend burst

current

H

X

X

X

H

H

H

Write, begin burst

external

L

H

L

H

L

X

L

Write, continue burst

next

X

X

X

H

H

L

L

Write, continue burst

next

H

X

X

X

H

L

L

Write, suspend burst

current

X

X

X

H

H

H

L

Write, suspend burst

current

H

X

X

X

H

H

L

Cycle

OE

DQ

Read

L

Q

Read

H

Hi-Z

Write

X

Hi-Z; D

Deselect

X

Hi-Z