Philips Semiconductors

Product specification

74ABT16821A

74ABTH16821A

20-bit bus-interface D-type flip-flop;

positive-edge trigger (3-State)

1998 Feb 27

5

DC ELECTRICAL CHARACTERISTICS

LIMITS

SYMBOL

PARAMETER

TEST CONDITIONS

to +85

°C

UNIT

Min

Typ

Max

Min

Max

Input clamp voltage

–0.9

–1.2

–1.2

V

2.5

2.9

2.5

V

High-level output voltage

3.0

3.4

3.0

V

2.0

2.4

2.0

V

Low-level output voltage

0.36

0.55

0.55

V

0.13

0.55

0.55

V

Input leakage current

±0.01

±1.0

±1.0

µA

In ut leakage current

±0.01

±1.0

±1.0

µA

Control pins

±0.01

±1

±1

µA

Input leakage current

74ABTH16821A

Data pins

0.01

1

1

µA

74ABTH16821A

Data pins

–1

–3

–5

µA

B

H ld

t i

35

35

74ABTH16821A

–75

–75

µA

±800

Power-off leakage current

±5.0

±100

±100

µA

Power-up/down 3-State

±5.0

±50

±50

µA

3-State output High current

1.0

10

10

µA

3-State output Low current

–1.0

–10

–10

µA

Output High leakage

current

5.0

50

50

µA

–50

–90

–180

–50

–180

mA

0.5

1

1

mA

Quiescent supply current

10

19

19

mA

0.5

1

1

mA

Additional supply current

0.25

1.5

1.5

mA

NOTES:

1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second.

2. This is the increase in supply current for each input at 3.4V.

3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power.

time of up to 100

µsec is permitted.

5. This is the bus hold overdrive current required to force the input to the opposite logic state.