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GS840FH36AGT-8I Datasheet(PDF) 7 Page - GSI Technology |
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GS840FH36AGT-8I Datasheet(HTML) 7 Page - GSI Technology |
7 / 21 page GS840FH18/32/36AT-8/8.5/10/12 Rev: 1.07 10/2004 7/21 © 1999, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Note: There is a pull-up device on the LBO pin and a pull down device on the ZZ pin, so those input pins can be unconnected and the chip will operate in the default states as specified in the above tables. Burst Counter Sequences Notes: 1. All byte outputs are active in read cycles regardless of the state of Byte Write Enable inputs. 2. Byte Write Enable inputs BA, BB, BC and/or BD may be used in any combination with BW to write single or multiple bytes. 3. All byte I/O’s remain High-Z during all write operations regardless of the state of Byte Write Enable inputs. 4. Bytes “C” and “D” are only available on the x32 and x36 versions. Mode Pin Functions Mode Name Pin Name State Function Burst Order Control LBO L Linear Burst H or NC Interleaved Burst Power Down Control ZZ L or NC Active H Standby, IDD = ISB Byte Write Truth Table Function GW BW BA BB BC BD Notes Read H H X X X X 1 Read H L HHHH 1 Write byte A H L L HHH 2, 3 Write byte B HLHLH H 2, 3 Write byte C H L H H L H 2, 3, 4 Write byte D H L HHH L 2, 3, 4 Write all bytes H LLLLL 2, 3, 4 Write all bytes L XXXX X Note: The burst counter wraps to initial state on the 5th clock. Note: The burst counter wraps to initial state on the 5th clock. A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 10 11 00 3rd address 10 11 00 01 4th address 11 00 01 10 A[1:0] A[1:0] A[1:0] A[1:0] 1st address 00 01 10 11 2nd address 01 00 11 10 3rd address 10 11 00 01 4th address 11 10 01 00 |
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