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GS8162Z72CGC-333 Datasheet(PDF) 20 Page - GSI Technology |
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GS8162Z72CGC-333 Datasheet(HTML) 20 Page - GSI Technology |
20 / 29 page GS8162Z72CC-333/300/250/200/150 Preliminary Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.01 3/2005 20/29 © 2004, GSI Technology device pins and the bits in the Boundary Scan Register is described in the Scan Order Table following. The Boundary Scan Register, under the control of the TAP Controller, is loaded with the contents of the RAMs I/O ring when the controller is in Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. JTAG TAP Block Diagram Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. Instruction Register ID Code Register Boundary Scan Register 0 1 2 0 ·· · · 31 30 29 1 2 0 Bypass Register TDI TDO TMS TCK Test Access Port (TAP) Controller · · · · · ··· · · Control Signals · |
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