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GS8170DW36AC-350 Datasheet(PDF) 11 Page - GSI Technology

Part No. GS8170DW36AC-350
Description  18Mb Σ1x1Dp CMOS I/O Double Late Write SigmaRAM
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Maker  GSI [GSI Technology]
Homepage  http://www.gsitechnology.com
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GS8170DW36/72AC-350/333/300/250
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
Rev: 1.04 4/2005
11/32
© 2003, GSI Technology
It should be noted that deselection of the RAM via E2 and E3 also deselects the Echo Clock output drivers. The deselection of
Echo Clock drivers is always pipelined to the same degree as output data. Deselection of the RAM via E1 does not deactivate the
Echo Clocks.
In some applications it may be appropriate to pause between banks; to deselect both RAMs with E1 before resuming read
operations. An E1 deselect at a bank switch will allow at least one clock to be issued from the new bank before the first read cycle
in the bank. Although the following drawing illustrates a E1 read pause upon switching from Bank 1 to Bank 2, a write to Bank 2
would have the same effect, causing the RAM in Bank 2 to issue at least one clock before it is needed.
Echo Clock Control in Two Banks of SigmaRAMs
Note: E1\ does not deselect the Echo Clock Outputs. Echo Clock outputs are synchronously deselected by E2 or E3 being sampled false.
QD
CQ
Bank 1
CQ
Bank 2
DQ
Bank 2
QB
CQ1 + CQ2
QC
Address
A
B
/E1
/E2 Bank 1
E2 Bank 2
DQ
Bank 1
QA
ADV
F
DE
C
Read
Read
Read
CK
Read
Read




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