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GS8170DD36C-200 Datasheet(PDF) 22 Page - GSI Technology |
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GS8170DD36C-200 Datasheet(HTML) 22 Page - GSI Technology |
22 / 29 page GS8170DD36C-333/300/250/200 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 2.03 1/2005 22/29 © 2002, GSI Technology, Inc. JTAG TAP Block Diagram Identification (ID) Register The ID Register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in Capture-DR state with the IDCODE command loaded in the Instruction Register. The code is loaded from a 32-bit on-chip ROM. It describes various attributes of the RAM as indicated below. The register is then placed between the TDI and TDO pins when the controller is moved into Shift-DR state. Bit 0 in the register is the LSB and the first to reach TDO when shifting begins. ID Register Contents Die Revision Code Not Used I/O Configuration GSI Technology JEDEC Vendor ID Code Bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x36 X X X X 0 000000 0000010 00 0 0 0 1 1 0 1 1 0 0 1 1 Instruction Register ID Code Register Boundary Scan Register 0 1 2 0 ·· · · 31 30 29 1 2 0 Bypass Register TDI TDO TMS TCK Test Access Port (TAP) Controller · · · · · ··· · · Control Signals · |
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