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TMC2081 Datasheet(PDF) 8 Page - Fairchild Semiconductor |
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TMC2081 Datasheet(HTML) 8 Page - Fairchild Semiconductor |
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8 / 32 page  TMC2081 PRODUCT SPECIFICATION 8 Table 10. GBR DAC Transfer Characteristic with Pedestal (SETUP = H) YCBCR Output Data inputs are unsigned Ydata and offset-binary format CBdata and CRdata. BLANK = L sets CB and CR outputs to 128, the value for zero chrominance data. YCBCR transfer equations are: Y = (Ydata + SETUP * 21) & BLANK + SYNC * 110 CB = (Cdata + SETUP * 21) & BLANK + 128 & !BLANK CR = (Cdata + SETUP * 21) & BLANK + 128 & !BLANK Sample outputs are listed in Table 11 and Table 12. Table 11. YCrCb DAC Transfer Characteristic without Pedestal (SETUP = L) Table 12. YCrCb DAC Transfer Characteristic with Pedestal (SETUP = H) D/A Input Data G B or R SYNC BLANK IU mV IU mV 255 1 1 386 1000 276 715 128 1 1 259 671 149 386 0 1 1 131 339 21 54 X 1 0 110 285 0 0 X0 0 0 0 0 0 128 0 1 149 386 149 386 D/A Input Data YCB or CR SYNC BLANK IU mV IU mV 255 1 1 365 1000 255 699 128 1 1 238 652 128. 351 64 1 1 174 477 64 175 0 1 1 110 301 0 0 X 1 0 110 301 128 351 X 0 0 0 0 128 351 64 0 1 64 175 64 175 D/A Y CB or CR Data SYNC BLANK IU mV IU mV 255 1 1 386 1000 276 715 128 1 1 259 670 149 386 64 1 1 195 505 85 220 0 1 1 131 339 21 54 X 1 0 110 285 149 386 X 0 0 0 0 149 386 64 0 1 85 220 85 220 Dissolve and Crossfade Operation Video transitions such as dissolve and fades may be executed by direct a-channel control. Rate and start time for the transition depends entirely upon the value of the a8-0 inputs. Transitions may be executed as quickly or slowly as values are presented to the a-channel. Transitions may remain partially executed by keeping a-values constant. It is possible to mix modes, bringing data in either 444 or 422 format and outputting data in 422 or 444 format. In the 444/444 mode (see Figure 7), a is applied to each YCBCR or GBR pixel pair at the input of the mixer. The YCBCR444 output is mixed at the full a rate. In the 422/422 mode (see Figure 8), a mixes the Y compo- nent of incoming PDA and PDB pixels. Only odd indexed a values mix CBCR components. a-values applied to CBCR change synchronously with CB data. Consequently, full bandwidth a data is applied to the luminance channel but the chrominance channel a values are decimated by dropping the even values that are synchronous with CR data. In the 422/444 mode (see Figure 9), YCBCR422 data is accepted at the PDA and PDB port but the output at the M23-0 port is YCBCR444. a may change from pixel-to-pixel with mixing at the M23-0 outputs tracking both Y and CBCR. Although odd values of CB and CR are repeated at half the pixel rate, a transitions are applied to CB and CR at the pixel rate. Microprocessor Interface Internal Control Registers, CLUT, aLUT, and the overlay palette are accessed through a bi-directional microprocessor port, D7-0. Table 13 shows how address bits, A2-0, select the registers to be accessed. Table 13. Microprocessor Port Address Map A2-0 Action 000 RAM Address Register for CLUT, aLUT, and overlay palette for write operations 001 Directs RAM R/W operations selected by the two MSBs of Control Address Register 010 Reserved 011 RAM Address Register for CLUT, aLUT, and overlay palette for read operations 100 Reserved 101 Directs Control Register R/W operations selected by the four LSBs of the Control Address Register 110 Mask Register (Default: Load with FF) 111 Control Address Register |
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Similar Description - TMC2081 |
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