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GS8180QV18D-100 Datasheet(PDF) 1 Page - GSI Technology |
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GS8180QV18D-100 Datasheet(HTML) 1 Page - GSI Technology |
1 / 32 page Rev: 2.03 10/2004 1/32 © 2002, GSI Technology Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8180QV18/36D-200/167/133/100* 18Mb Burst of 2 SigmaQuad SRAM 200 MHz–100 MHz* 2.5 V VDD 1.8 V or 1.5 V I/O 165-Bump BGA Commercial Temp Industrial Temp Features • Simultaneous Read and Write SigmaQuad™ Interface • JEDEC-standard pinout and package • Dual DoubleData Rate interface • Byte Write controls sampled at data-in time • Burst of 2 Read and Write • 2.5 V +100/–100 mV core power supply • 1.5 V or 1.8 V HSTL Interface • Pipelined read operation • Fully coherent read and write pipelines • ZQ mode pin for programmable output drive strength • IEEE 1149.1 JTAG-compliant Boundary Scan • 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package • Pin-compatible with future 36Mb, 72Mb, and 144Mb devices SigmaRAM™ Family Overview GS8180QV18 are built in compliance with the SigmaQuad SRAM pinout standard for Separate I/O synchronous SRAMs. They are18,874,368-bit (18Mb) SRAMs. These are the first in a family of wide, very low voltage HSTL I/O SRAMs designed to operate at the speeds needed to implement economical high performance networking systems. SigmaQuad SRAMs are offered in a number of configurations. Some emulate and enhance other synchronous separate I/O SRAMs. A higher performance SDR (Single Data Rate) Burst of 2 version is also offered. The logical differences between the protocols employed by these RAMs hinge mainly on various combinations of address bursting, output data registering, and write cueing. Along with the Common I/O family of SigmaRAMs, the SigmaQuad family of SRAMs allows a user to implement the interface protocol best suited to the task at hand. Clocking and Addressing Schemes A Burst of 2 SigmaQuad SRAM is a synchronous device. It employs two input register clock inputs, K and K. K and K are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. The device also allows the user to manipulate the output register clock inputs quasi independently with the C and C clock inputs. C and C are also independent single-ended clock inputs, not differential inputs. If the C clocks are tied high, the K clocks are routed internally to fire the output registers instead. Because Separate I/O Burst of 2 RAMs always transfer data in two packets, A0 is internally set to 0 for the first read or write transfer, and automatically incremented by 1 for the next transfer. Because the LSB is tied off internally, the address field of a Burst of 2 RAM is always one address pin less than the advertised index depth (e.g., the 1M x 18 has a 512K addressable index). *x18 part available in 200/167/133/100 MHz speeds; x36 part available in 133/100 MHz Parameter Synopsis* -200 -167 -133 -100 tKHKH 5.0 ns 6.0 ns 7.5 ns 10.0 ns tKHQV 2.3 ns 2.5 ns 3.0 ns 3.0 ns |
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