Preliminary

GS8182Q18D-200/167/133

18Mb Burst of 2

SigmaQuad-II SRAM

200MHz–133MHz

1.8 V and 1.5 V I/O

165-Bump BGA

Commercial Temp

Industrial Temp

Rev: 1.02 11/2004

1/28

© 2003, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Features

• Simultaneous Read and Write SigmaQuad™ Interface

• JEDEC-standard pinout and package

• Dual Double Data Rate interface

• Byte Write controls sampled at data-in time

• Burst of 2 Read and Write

• 1.8 V +150/–100 mV core power supply

• 1.5 V or 1.8 V HSTL Interface

• Pipelined read operation

• Fully coherent read and write pipelines

• ZQ mode pin for programmable output drive strength

• IEEE 1149.1 JTAG-compliant Boundary Scan

• 165-bump, 13 mm x 15 mm, 1 mm bump pitch BGA package

• Pin-compatible with future 36Mb, 72Mb, and 144Mb devices

SigmaRAM™ Family Overview

GS8182Q18 are built in compliance with the SigmaQuad-II

SRAM pinout standard for Separate I/O synchronous SRAMs.

They are 18,874,368-bit (18Mb) SRAMs. These are the first in

a family of wide, very low voltage HSTL I/O SRAMs designed

to operate at the speeds needed to implement economical high

performance networking systems.

Clocking and Addressing Schemes

A Burst of 2 SigmaQuad-II SRAM is a synchronous device. It

employs two input register clock inputs, K and K. K and K are

independent single-ended clock inputs, not differential inputs

to a single differential clock input buffer. The device also

allows the user to manipulate the output register clock inputs

quasi independently with the C and C clock inputs. C and C are

also independent single-ended clock inputs, not differential

inputs. If the C clocks are tied high, the K clocks are routed

internally to fire the output registers instead.

Because Separate I/O Burst of 2 RAMs always transfer data in

two packets, A0 is internally set to 0 for the first read or write

transfer, and automatically incremented by 1 for the next

transfer. Because the LSB is tied off internally, the address

field of a Burst of 2 RAM is always one address pin less than

the advertised index depth (e.g., the 1M x 18 has a 512K

addressable index).

Parameter Synopsis

-200

-167

-133

tKHKH

5.0 ns

6.0 ns

7.5 ns

tKHQV

0.45 ns

0.5 ns

0.5 ns

165-Bump, 13 mm x 15 mm BGA

1 mm Bump Pitch, 11 x 15 Bump Array

Bottom View

JEDEC Std. MO-216, Variation CAB-1