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GS8182Q18D-133I Datasheet(PDF) 5 Page - GSI Technology |
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GS8182Q18D-133I Datasheet(HTML) 5 Page - GSI Technology |
5 / 28 page Preliminary GS8182Q18D-200/167/133 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Rev: 1.02 11/2004 5/28 © 2003, GSI Technology SigmaQuad-II B2 SRAM DDR Read The read port samples the status of the Address Input and R pins at each rising edge of K. A low on the Read Enable-bar pin, R, begins a read cycle. Data can be clocked out after the next rising edge of K with a rising edge of C (or by K if C and C are tied high), and after the following rising edge of K with a rising edge of C (or by K if C and C are tied high). Clocking in a high on the Read Enable-bar pin, R, begins a read port deselect cycle. Burst of 2 Double Data Rate SigmaQuad-II SRAM Read First Read A NOP Write B Read C Write D Read E Write F Read G Write H NOP A B C D E F G H B B+1 D D+1 F F+1 H H+1 A A+1 C C+1 E E+1 G K K Address R W BWx D C C Q CQ CQ |
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