GS8180QV18/36D-200/167/133/100*

Rev: 2.03 10/2004

10/32

© 2002, GSI Technology

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

FLXDrive-II Output Driver Impedance Control

via an external resistor, RQ, to allow the SRAM to monitor and adjust its output driver impedance. The value of RQ must be 5X the

value of the intended line impedance driven by the SRAM. The allowable range of RQ to guarantee impedance matching with a

vendor-specified tolerance is between 150

Ω and 300Ω. Periodic readjustment of the output driver impedance is necessary as the

impedance is affected by drifts in supply voltage and temperature. A clock cycle counter periodically triggers an impedance

evaluation, resets and counts again. Each impedance evaluation may move the output driver impedance level one step at a time

towards the optimum level. The output driver is implemented with discrete binary weighted impedance steps. The SRAM requires

Burst of 2 Coherency and Pass Through Functions

Because the Burst of 2 read and write commands are loaded at the same time, there may be some confusion over what constitutes

“coherent” operation. Normally, one would expect a RAM to produce the just-written data when it is read immediately after a

write. This is true of the Burst of 2 except in one case, as is illustrated in the following diagram. If the user holds the same address

value in a given K clock cycle, loading the same address as a read address and then as a matching write address, the Burst of 2 will

read or “Pass-thru” the latest data input, rather than the data from the previously completed write operation.

Burst of 2 Coherency and Pass Through Functions

Dwg Rev. G

DB0

DB1

DD0

DD1

DF0

DF1

DH0

DH1

DI0

QA0

QA1

QC0

QC1

QE0

QE1

71

Write

Read

OO

IO

56

OI

3

Write

Read

Write

C

/R

/W

/BWx

Read

Write

Address

OO

OI

OI

OO

OO

OO

Read

K

/K

D

Q

??

5

/C

4

682

719

HI

ABCD

E

F

G

COHERENT

PASS-THRU